RX IF/BBA WITH AGC
S1M8656A
INTRODUCTION
48-LQFP-0707
S1M8656A/8657 are CDMA/AMPS Dual Mode IF/ baseband IC which is
divided into three main parts - IF frequency processing, basband
processing , and digital interface. The receiver IC (S1M8656A)and
transmitter IC (S1M8657) are provided as a KIT.
S1M8656A is a receiver IC, installed with a Rx AGC, Baseband
Converter, Baseband analog filter, and A-D Converter. It can send a
digital baseband signal to the digital baseband IC. The S1M8657X01 is a
transmission-only IC, installed with a Tx AGC, IF frequency converter,
analog filter, D-A Converter, PLL, 8-bit A-D Converter for the system
monitor, and 3-input analog switch. It connects the digital baseband IC to
the RF processing. Designed to operate in direction connection with the
MSM, S1M8656A and S1M8657 are fabricated on the Samsung's 0.5um
high-speed, high-frequency BICMOS processing and can achieve
superior high frequency and low power digital operations.
Its operating voltage is 2.7V – 3.6V, and operating temperature
-30°C – +85°C .
48-BCC-7.0
×
7.0
FEATURES
•
•
•
•
•
•
•
•
•
•
CDMA/AMPS Dual Mode
AGC input signal range : 90dB
QPSK Baseband Converter
Built-in I ,Q Baseband signal extractor LPF
Built-in 4-bit ADC for converting I and Q CDMA analog baseband signals to digital baseband signals
Built-in 8-bit ADC for converting I and Q FM analog baseband signals to digital baseband signals
Adopts the Rx SLOT function to minimize the AMPS Mode consumption power
Built-in VCO for baseband conversion
Built-in Modem PDM control circuit to compensate the I and Q offsets
3-Line Serial Port Interface (SPI)
ORDERING INFORMATION
Device
+ S1M8656A01-E0T0
+ S1M8656A01-F0T0
+ : New product
Package
48-LQFP-0707
48-BCC-7.0×7.0
Operating Temperature
-30 to +85
°
C
1
S1M8656A
RX IF/BBA WITH AGC
BLOCK DIAGRAM
I_OFS
Q_OFS
TCXO
DIV.N/CHIPx8
TCXO/N
CHIPx8
FMCLK
FMSTB
FMRID/RXID1
FMRQD/RXID0
2
2
4
CRX_IF1
CRX_IF2
RAGC_CONT
FRX_IF1
FRX_IF2
1/2Div.
90D-PSN
LPF
LPF
LPF
LPF
OFFSET
CONTROL
OFFSET
CONTROL
OFFSET
CONTROL
OFFSET
CONTROL
ADC
ADC
ADC
ADC
SW
SW
4
RXID2-3
RXQD0-3
3-line Serial Port Interface
MODE Control
RXVCO_T2
RXVCO_OUT
RXVCO_T1
SLEEPB/CLK
FMB/DATA
IDLEB/STB
SLOTB
2
SEN
RX IF/BBA WITH AGC
S1M8656A
PIN CONFIGURATION
FMRQD/RXID0
FMRID/RXID1
48
47
46
45
44
43
42
41
40
39
38
37
TCXO/N
RXQD0
RXQD1
RXQD2
RXQD3
CHIPx8
RXID2
RXID3
GND
VDD
FMCLK
FMSTB
GND
VCC
GND
VCC
RAGC_CONT
GND
FRX_IF1
FRX_IF2
CRX_IF1
CRX_IF2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
TCXO
VCC
GND
N.C
SLEEPB/CLK
FMB/DATA
IDLEB/STB
SLOTB
I_OFS
Q_OFS
SEN
RXVCO_OUT
S1M8656A
31
30
29
28
27
26
25
RXVCO_T1
RXVCO_T2
GND
GND
N.C
GND
GND
VCC
VCC
VCC
VCC
VCC
3
S1M8656A
RX IF/BBA WITH AGC
PIN DESCRIPTION
Pin No
1
2
Symbol
FMCLK
FMSTB
I/O
SEN
DI
Description
FM ADC clock input ,received from the modem.
Signal frequency is 360kHz; if unconnected, it becomes LOW.
FM STROBE input. Signal that controls the FM ADC initialization and
A-D conversion start. CLOCK frequency is 40kHz, which is received
from the MODEM; if unconnected, it remains at LOW.
AGC gain control input. The input voltage is allowed up to V
DD
.
It remains at High impedance during SLEEP.
FM IF input terminals, which have an input impedance of about 865Ω;
generally, the FM IF SAW filter is connected to them. Usually, the IF
SAW output is single-ended.
When these terminals are not used, they remain at High impedance.
CDMA IF input terminals, which have an input impedance of about
865Ω; generally, the CDMA IF SAW filter is connected to them.
Usually, the IF SAW output is differential. When these terminals are
not used, they remain at High impedance.
Very sensitive terminal, which is connected to the oscillation L-C
resonance circuit.
Their impedance are about 2kΩ
Output for the PLL, able to output about -12dBm.
When this is not used, it remains at high impedance.
Input that permits/not permits SPI BUS control.
If the input is high, SPI control is allowed, and its related 3-pins, STB,
DATA, and CLK, perform their functions; if Low, related 3-pins,
IDLEB, FMB, and SLEEPB, are allowed to perform parallel control.
When this is not used, it remains at Low.
Control DC input for removing the DC offset generated in the BBA
and system during CDMA and AMPS Mode. The control DC is
generated in the modem in PDM form, passes through the R-C filter
and is converted to DC, which is sent to this input terminal. No pull
up/down should be performed at this terminal.
This pin becomes Low during CDMA SLEEP Mode or FM RX Mode,
the system is assumed to be in the Rx SLOT mode, and all functions
are stopped except for the VCO, VCO buffer and TCXO/N. No
external clock inputs are not required in this product with this function.
When SEN is high, this pin becomes the STROBE input with the
permit of the 3-LINE Serial control input.
When SEN is low, parallel control input is allowed and this pin
executes the IDLEB function. If this pin is opened, it remains at Low.
When SEN is high, this pin inputs and outputs data with the permit of
the 3-line serial control input. When SEN is low, parallel control input
is allowed and this pin performs IDLEB. If this pin is opened, it
remains at Low.
7
9
10
RAGC_CONT
FRX_IF1
FRX_IF2
AI
AI
11
12
CRX_IF1
CRX_IF2
AI
21
22
25
26
RXVCO_T1
RXVCO_T2
RXVCO_OUT
SEN
AI
AO
D
27
28
Q_OFS
I_OFS
AI
29
SLOTB
DI
30
IDLEB/STB
DI
31
FMB/DATA
BI
4
RX IF/BBA WITH AGC
S1M8656A
PIN DESCRIPTION (Continued)
Pin No
32
Symbol
SLEEPB/CLK
I/O
DI
Description
When SEN is high, this pin inputs the clock with the permit of the 3-
line serial control input. When SEN is low, parallel control input is
allowed and this pin performs SLEEPB. If this pin is opened, it
remains at Low.
Reference frequency input terminal connected to the VCTCXO output.
When this pin stops, only DC bias is delivered to maintain the DC
charge value of the capacitor connected externally.
Division output of the TCXO Reference frequency input. 3-different
division ratio and 2- output drive capacities can be selected through
the SPI bus control. Default : 4.92MHz, Weak OUT *division ratio : 1,
1/4, 1/16
CHIPx8 CLOCK output terminal. It has a division ratio of 512/1025 for
the TCXO reference frequency.
Therefore, it cannot have a perfect 50% duty. When this terminal is
not used (CDMA SLEEP, FM IDLE), it remains at Low. This pin can
be used exclusively for the externally generated CHIPx8 CLOCK input
using the SPI BUS control.
CDMA A-D Converter's digital outputs, which are connected to the
modem data input pins. These data are synchronized at CHIPx8's
rising edge and output. Because they are valid at the falling edge, the
data are latched at the falling edge in the modem.
Because the number of 48-pins are restricted in this product, pins 47
and 48 are shared with the FMDATA pin.
36
TCXO
AI
37
TCXO/N
DO
38
CHIPx8
BI
39
40
41
42
45
46
47
48
4, 6,
14,
15, 17,
20, 24
35
44
3, 5, 8,
13, 16,
18, 19,
23, 43
34
33
RXQD3
RXQD2
RXQD1
RXQD0
RXID3
RXID2
RXID1/FMRID
RXID0/FMRQD
VCC
DO
AI
Power input terminal for the analog circuit.
VDD
VDD
GNDA
DI
DI
AI
Power for the digital logic.
Power source for a logic circuit ,related to the digital input /output,
connected to an external digital logic such as the modem.
Analog circuit ground.
Pin-18 is N.C. in the product.
GNDD
NC
DI
-
Digital logic circuit ground.
This pin is used for internal testing only and is not connected to
anything.
5
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