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Z9952: Description3.3V, 180MHz, Multi-Output Zero Delay Buffer; File Size45KB，9 Pages; ManufacturerCypress Semiconductor

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3.3V, 180MHz, Multi-Output Zero Delay Buffer

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Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Product Features

•

180MHz Clock Support

150ps Maximum Output to Output Skew

Supports PowerPC , Intel and RISC Processors

11 Clock Outputs: Frequency Configurable

Outputs Drive up to 22 Clock Lines

LVCMOS/LVTTL Compatible Inputs

Output Tri-state Control

Spread Spectrum Compatible

3.3V Power Supply

Pin Compatible with MPC952

Industrial Temp. Range: -40°C to +85°C

32-Pin TQFP Package

Frequency Table

VCO_SEL

SEL (A:C)

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

QA(0:4)

VCO/4

VCO/6

VCO/8

VCO/12

Table 1

QB(0:3)

VCO/4

VCO/2

VCO/4

VCO/2

VCO/8

VCO/4

VCO/8

VCO/4

QC (0,1)

VCO/2

VCO/4

VCO/2

VCO/4

VCO/2

VCO/4

VCO/2

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

Block Diagram

PLL_EN#

REFCLK

FB_IN

LPF

Phase

Detector

VCO

200-480M

/4,

QA0

QA1

QA2

QA3

QA4

Pin Configuration

VCO_SEL

SELA

/4,

VDDC

QB0

QB1

SELB

QB2

QB3

/2,

QC0

QC1

PLL_EN#

QA0

VSS

QA1

VDDA

QA2

Figure 1

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

VDDC

VDD

SELC

MR/OE#

VCO_SEL

SELC

SELB

SELA

MR/OE#

REFCLK

VSS

FB_IN

VDDC

QC1

QC0

QB3

QB2

VSS

Z9952

VSS

QB1

QB0

VDDC

QA4

QA3

VSS

12/22/2002

Page 1 of 9

Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Description

The Z9952 has an integrated PLL that provides low skew and low jitter clock outputs for high performance

microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480

MHz. This allows a wide range of output frequencies up to 180MHz. The Z9952 features three banks of individually

configurable outputs: Bank A five outputs, Bank B four outputs, and Bank C two outputs. When MR/OE# input is set

high, all the outputs are tri-stated. The Z9952 outputs are LVCMOS compatible and can drive two series terminated 50Ω

transmission lines. With this capability the Z9952 has an effective fanout of 1:22. Low output-to-output skews make the

Z9952 ideal for clock distribution in nested clock trees in the most demanding of synchronous systems.

The phase detector compares the input reference clock to the external feedback input. For normal operation, the

external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input

reference clock set by SEL(A:C) select inputs, see Table 2. The VCO_SEL input allows for the choice of two VCO

ranges to optimize PLL stability and jitter performance, see Table 1. The VCO frequency is then divided down to provide

the required output frequencies. The use of even dividers ensures that the output duty cycle remains at 50%.

SELA

÷4

÷6

SELB

÷4

÷2

SELC

÷2

÷4

Table 2

Zero Delay Buffer

When used as a zero delay buffer the Z9952 will likely be in a nested clock tree application. Any of the eleven outputs

can be used as the feedback to the PLL. By using one of the outputs as a feedback to the PLL the propagation delay

through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a

near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between

the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the Z9952 is a

function of the configuration used.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

12/22/2002

Page 5 of 9

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