PRELIMINARY
K6T1008C2C Family
Document Title
128K x8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
0.1
History
Initial draft
First revision
- Seperate read and write at I
CC
, I
CC1
I
CC =
I
CC1
→
Read : 15mA, Write : 35mA
Finalized
- Add 70ns speed bin for commercial product and 85ns speed
bin for industrial.
Revised
- Improved operating current
Add typical value.
I
CC
Read : 15mA
→
10mA(Remove write current)
I
CC2
: 90mA
→
60mA
- Speed bin change
Remove 45ns from commercial part
Remove 55ns and 100ns from industrial part.
Draft Date
November 22, 1995
April 15, 1996
Remark
Design target
Preliminary
1.0
September 5, 1996
Final
2.0
November 5, 1997
Final
The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
November 1997
PRELIMINARY
K6T1008C2C Family
128K x8 bit Low Power CMOS Static RAM
FEATURES
•
Process Technology: TFT
•
Organization: 128K x8
•
Power Supply Voltage: 4.5~5.5V
•
Low Data Retention Voltage: 2V(Min)
•
Three state output and TTL Compatible
•
Package Type: 32-DIP-600, 32-SOP-525,
32-TSOP1-0820F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6T1008C2C families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and have various
package types for user flexibility of system design. The fami-
lies also support low data retention voltage for battery back-
up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
Standby
(I
SB1
, Max)
50µA
10µA
60mA
70ns
50µA
15µA
32-SOP
32-TSOP1-F/R
Operating
(I
CC2
, Max)
PKG Type
K6T1008C2C-L
K6T1008C2C-B
K6T1008C2C-P
K6T1008C2C-F
Commercial(0~70°C)
4.5~5.5V
Industrial(-40~85°C)
55/70ns
32-DIP, 32-SOP
32-TSOP1-F/R
PIN DESCRIPTION
A11
A9
A8
VCC A13
WE
A15
CS2
CS2 A15
VCC
WE
N.C
A13 A16
A14
A8
A12
A9
A7
A6
A11
A5
OE
A4
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A4
A5
A6
A7
A12
A14
A16
N.C
VCC
A15
CS2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
FUNCTIONAL BLOCK DIAGRAM
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
Clk gen.
Precharge circuit.
N.C
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
A4
A5
A6
A7
A8
A12
A13
A14
A15
A16
V
CC
V
SS
Memory array
1024 rows
128×8 columns
32-TSOP
Type1 - Forward
25
24
23
22
21
20
19
18
17
Row
select
32-DIP
32-SOP
25
24
23
22
21
20
19
18
17
32-TSOP
Type1 - Reverse
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE
CS1
CS2
I/O
1
I/O
8
Data
cont
I/O Circuit
Column select
Data
cont
A0
A1
A2
A3 A9 A10 A11
Name
CS
1
,CS
2
OE
WE
A
0
~A
16
Function
Chip Select Inputs
Output Enable
Write Enable Input
Address Inputs
Name
I/O
1
~I/O
8
Vcc
Vss
N.C
Function
Data Inputs/Outputs
Power
Ground
No Connection
WE
OE
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 2.0
November 1997
PRELIMINARY
K6T1008C2C Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
K6T1008C2C-DL55
K6T1008C2C-DL70
K6T1008C2C-DB55
K6T1008C2C-DB70
K6T1008C2C-GL55
K6T1008C2C-GL70
K6T1008C2C-GB55
K6T1008C2C-GB70
K6T1008C2C-TB55
K6T1008C2C-TB70
K6T1008C2C-RB55
K6T1008C2C-RB70
Function
32-DIP, 55ns, L-pwr
32-DIP, 70ns, L-pwr
32-DIP, 55ns, LL-pwr
32-DIP, 70ns, LL-pwr
32-SOP, 55ns, L-pwr
32-SOP, 70ns, L-pwr
32-SOP, 55ns, LL-pwr
32-SOP, 70ns, LL-pwr
32-TSOP1-F, 55ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
32-TSOP1-R, 55ns, LL-pwr
32-TSOP1-R, 70ns, LL-pwr
Industrial Temperature Products(-40~85°C)
Part Name
K6T1008C2C-GP70
K6T1008C2C-GF70
K6T1008C2C-TF70
K6T1008C2C-RF70
Function
32-SOP, 70ns, L-pwr
32-SOP, 70ns, LL-pwr
32-TSOP1-F, 70ns, LL-pwr
32-TSOP1-R, 70ns, LL-pwr
CMOS SRAM
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O Pin
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disable
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care(Must be in high or low status.)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Soldering temperature and time
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
SOLDER
Ratings
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
260°C, 10sec (Lead Only)
Unit
V
V
W
°C
°C
°C
-
Remark
-
-
-
-
K6T1008C2C-L
K6T1008C2C-P
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 2.0
November 1997
PRELIMINARY
K6T1008C2C Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
4.5
0
2.2
-0.5
3)
Typ
5.0
0
-
-
Max
5.5
0
Vcc+0.5
2)
0.8
Unit
V
V
V
V
CMOS SRAM
Note
1. Commercial Product : T
A
=0 to 70°C and Industrial Product :T
A
=-40 to 85°C, otherwise specified.
2. Overshoot : Vcc+3.0V for≤30ns pulse width.
3. Undershoot : -3.0V for≤30ns pulse width.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1
)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled not, 100% tested.
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
6
8
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
K6T1008C2C-L
Standby
Current
(CMOS)
K6T1008C2C-B
K6T1008C2C-P
K6T1008C2C-F
I
SB1
V
OL
V
OH
I
SB
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL,
V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IH
or V
IL
, Read
Cycle time=1µs, 100% duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥V
CC
-0.2V, V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Read
Write
-
-
2.4
-
-
-
-
-
Test Conditions
Min
-1
-1
-
-
Typ
-
-
5
2
20
45
-
-
-
1
0.3
1
0.3
Max
1
1
10
5
35
60
0.4
-
3
50
10
50
15
µA
mA
V
V
mA
Unit
µA
µA
mA
mA
Cycle time=Min, 100% duty, I
IO
=0mA, CS1=V
IL
, CS2=V
IH,
V
IN
=V
IL
or V
IH
I
OL
=2.1mA
I
OH
=-1.0mA
CS
1
=V
IH,
CS
2
=V
IL,
Other input=V
IL
or V
IH
CS
1
≥Vcc-0.2V,
CS2≥Vcc-0.2V
or CS
2
≤0.2V
Other input =0~Vcc
Low Power
Low Low Power
Low power
Low Low Power
4
Revision 2.0
November 1997
PRELIMINARY
K6T1008C2C Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1,
t
CO2
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1,
t
WR2
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
25
0
5
55ns
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Symbol
V
DR
Test Condition
CS
1
1)
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V
K6T1008C2C-L
Data retention current
I
DR
Vcc=3.0V, CS
1
≥Vcc-0.2V,
CS2≥Vcc-0.2V or CS
2
≤0.2V
K6T1008C2C-B
K6T1008C2C-P
K6T1008C2C-F
Data retention set-up
Recovery time
t
SDR
t
RDR
See data retention waveform
Min
2.0
-
-
-
-
0
5
Typ
-
1
1
-
-
-
-
Max
5.5
20
10
25
10
-
-
ms
µA
Unit
V
1. CS
1
≥Vcc-0.2v,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V
5
Revision 2.0
November 1997
FPGA/CPLD
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