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74AHC132PW-Q100

Description
IC NAND GATE, Gate
Categorylogic    logic   
File Size155KB,18 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

74AHC132PW-Q100 Overview

IC NAND GATE, Gate

74AHC132PW-Q100 Parametric

Parameter NameAttribute value
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts14
Reach Compliance Codeunknown
seriesAHC/VHC/H/U/V
JESD-30 codeR-PDSO-G14
length5 mm
Logic integrated circuit typeNAND GATE
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)19.5 ns
Filter levelAEC-Q100
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width4.4 mm
Base Number Matches1
74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
Rev. 1 — 8 November 2013
Product data sheet
1. General description
The 74AHC132-Q100; 74AHCT132-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A.
The 74AHC132-Q100; 74AHCT132-Q100 contains four 2-input NAND gates which accept
standard input signals. They can transform slowly changing input signals into sharply
defined, jitter free output signals. The gate switches at different points for positive-going
and negative-going signals. The difference between the positive voltage V
T+
and the
negative V
T
is defined as the hysteresis voltage V
H
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
Inputs accept voltages higher than V
CC
Input levels:
For 74AHC132-Q100: CMOS level
For 74AHCT132-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
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