MM74C90 • MM74C93 4-Bit Decade Counter • 4-Bit Binary Counter
October 1987
Revised May 2002
MM74C90 • MM74C93
4-Bit Decade Counter • 4-Bit Binary Counter
General Description
The MM74C90 decade counter and the MM74C93 binary
counter and complementary MOS (CMOS) integrated cir-
cuits constructed with N- and P-channel enhancement
mode transistors. The 4-bit decade counter can reset to
zero or preset to nine by applying appropriate logic level on
the R
01
, R
02
, R
91
and R
92
inputs. Also, a separate flip-flop
on the A-bit enables the user to operate it as a divide-by-2,
5 or 10 frequency counter. The 4-bit binary counter can be
reset to zero by applying high logic level on inputs R
01
and
R
02
, and a separate flip-flop on the A-bit enables the user
to operate it as a divide-by-2, -8, or -16 divider. Counting
occurs on the negative going edge of the input pulse.
All inputs are protected against static discharge damage.
Features
s
Wide supply voltage range:
3V to 15V
s
Guaranteed noise margin: 1V
s
High noise immunity: 0.45 V
CC
(typ.)
s
Low power compatibility:
Fan out of 2 TTL driving 74L
s
The MM74C93 follows the MM74L93 Pinout
Ordering Code:
Order Number
MM74C90N
MM74C93N
Package Number
N14A
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagrams
MM74C90
MM74C93
Top View
Top View
© 2002 Fairchild Semiconductor Corporation
DS005889
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MM74C90 • MM74C93
Logic Diagrams
MM74C90
MM74C93
Truth Tables
MM74C90 4-Bit Decade Counter BCD Count Sequence
Count
Q
D
0
1
2
3
4
5
6
7
8
9
L
L
L
L
L
L
L
L
H
H
Output
Q
C
L
L
L
L
H
H
H
H
L
L
Q
B
L
L
H
H
L
L
H
H
L
L
Q
A
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MM74C93 4-Bit Binary Counter Binary Count Sequence
Count
Q
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Output
Q
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Q
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Q
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Output Q
A
is connected to Input B for BCD count.
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
Output Q
A
is connected to input B for binary count sequence.
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
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2
MM74C90 • MM74C93
Function Tables
Reset/Count Function Table
Reset Inputs
R
01
H
H
X
X
L
L
X
R
02
H
H
X
L
X
X
L
R
91
L
X
H
X
L
X
L
R
92
X
L
H
L
X
L
X
Q
D
L
L
H
Output
Q
C
L
L
L
Count
Count
Count
Count
Q
B
L
L
L
Q
A
L
L
H
Reset/Count Function Table
Reset
Inputs
R
01
H
L
X
R
02
H
X
L
Q
D
L
Q
C
L
Count
Count
Q
B
L
Q
A
L
Output
3
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MM74C90 • MM74C93
Absolute Maximum Ratings
(Note 1)
Voltage at Any Pin (Note 1)
Operating Temperature Range (T
A
)
MM74C90, MM74C93
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Operating V
CC
Range
Absolute Maximum V
CC
Storage Temperature Range (T
S
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
700 mW
500 mW
3V to 15V
18V
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range”, they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
−
0.3V to V
CC
+
0.3V
−
55
°
C to
+
125
°
C
−
65
°
C to
+
150
°
C
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
Logical “1” Input Current
Logical “0” Input Current
Supply Current
Logical “1” Input Voltage
MM74C90, MM74C93
Logical “0” Input Voltage
MM74C90, MM74C93
Logical “1” Output Voltage
MM74C90, MM74C93
Logical “0” Output Voltage
MM74C90, MM74C93
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Output Source Current
(P-Channel)
Output Source Current
(P-Channel)
Output Sink Current
(N-Channel)
Output Sink Current
(N-Channel)
V
CC
=
4.75V, I
O
= −360 µA
V
CC
=
5V, V
OUT
=
0V
T
A
=
25°C
V
CC
=
10V, V
OUT
=
0V
T
A
=
25°C
V
CC
=
5V, V
OUT
=
V
CC
T
A
=
25°C
V
CC
=
10V, V
OUT
=
V
CC
T
A
=
25°C
0.4
V
V
CC
=
4.75V, I
O
= −360 µA
2.4
V
V
CC
=
4.75V
0.8
V
V
CC
=
4.75V
V
CC
−1.5
V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V, I
O
= −10 µA
V
CC
=
10V, I
O
= −10 µA
V
CC
=
5V, I
O
= +10 µA
V
CC
=
10V, I
O
= +10 µA
V
CC
=
15V, V
IN
=
15V
V
CC
=
15V, V
IN
=
0V
V
CC
=
15V
−1.0
0.005
−0.005
0.05
300
4.5
9.0
0.5
1.0
1.0
3.5
8.0
1.5
2.0
V
V
V
V
µA
µA
µA
Min
Typ
Max
Units
CMOS/LPTTL INTERFACE
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
−1.75
−8.0
1.75
8.0
−3.3
−15
3.6
16
mA
mA
mA
mA
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4
MM74C90 • MM74C93
AC Electrical Characteristics
T
A
=
25
°
C, C
L
=
50 pF, unless otherwise specified
Symbol
Parameter
t
pd0
, t
pd1
t
pd0
, t
pd1
t
pd0
, t
pd1
t
pd0
, t
pd1
t
pd0
, t
pd1
t
pd0
, t
pd1
t
pd0
, t
pd1
t
pd0
, t
pd1
Propagation Delay Time
from A
IN
to Q
A
Propagation Delay Time from
A
IN
to Q
B
(MM74C93)
Propagation Delay Time from
A
IN
to Q
B
(MM74C90)
Propagation Delay Time
from A
IN
to Q
C
(MM74C93)
Propagation Delay Time from
A
IN
to Q
C
(MM74C93)
Propagation Delay Time from
A
IN
to Q
D
(MM74C93)
Propagation Delay Time from
A
IN
to Q
D
(MM74C90)
Propagation Delay Time from
R
01
or R
02
to Q
A
, Q
B
, Q
C
or Q
D
(MM74C93)
t
pd0
, t
pd1
Propagation Delay Time from
R
01
or R
02
to Q
A
, Q
B
, Q
C
or Q
D
(MM74C90)
t
pd0
, t
pd1
Propagation Delay Time from
R
91
or R
92
to Q
A
or Q
D
(MM74C90)
t
PW
t
PW
t
PW
t
r
, t
f
t
W
f
MAX
C
IN
C
PD
Min. R
01
or R
02
Pulse Width
(MM74C93)
Min. R
01
or R
02
Pulse Width
(MM74C90)
Min. R
91
or R
92
Pulse Width
(MM74C90)
Maximum Clock Rise
and Fall Time
Minimum Clock Pulse Width
Maximum Clock Frequency
Input Capacitance
Power Dissipation Capacitance
(Note 2)
Conditions
Min
Typ
200
80
450
160
450
160
500
200
500
200
600
250
450
160
150
75
200
75
250
100
600
30
600
300
500
250
250
125
250
125
200
100
15
5
250
100
2
5
5
45
100
50
Max
400
150
850
300
800
300
1050
400
1000
400
1200
500
800
300
300
150
400
150
500
200
Units
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
=
5V
V
CC
=
10
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
10V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
Any Input (Note 3)
Per Package (Note 4)
ns
ns
ns
ns
ns
µs
ns
MHz
pF
pF
Note 2:
AC Parameters are guaranteed by DC correlated testing.
Note 3:
Capacitance is guaranteed by periodic testing.
Note 4:
C
PD
determines the no load ac power consumption of any CMOS device. For complete explanation see Family Characteristics application note—
AN-90.
5
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