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MM74C93

Description
CMOS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14
Categorysemiconductor    logic   
File Size69KB,8 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

MM74C93 Overview

CMOS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14

MM74C93 Parametric

Parameter NameAttribute value
Number of functions2
Number of terminals14
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage15 V
Minimum supply/operating voltage3 V
Rated supply voltage5 V
Processing package descriptionPLASTIC, DIP-14
stateTRANSFERRED
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeIN-LINE
Terminal formTHROUGH-HOLE
Terminal spacing2.54 mm
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
seriesCMOS
Counting directionUP
Load preset inputASYN PRESET
Logic IC typeDECADE COUNTER
Operating modeASYN
Number of digits3
propagation delay TPD400 ns
Trigger typeNEGATIVE EDGE
Max-Min frequency2 MHz
MM74C90 • MM74C93 4-Bit Decade Counter • 4-Bit Binary Counter
October 1987
Revised May 2002
MM74C90 • MM74C93
4-Bit Decade Counter • 4-Bit Binary Counter
General Description
The MM74C90 decade counter and the MM74C93 binary
counter and complementary MOS (CMOS) integrated cir-
cuits constructed with N- and P-channel enhancement
mode transistors. The 4-bit decade counter can reset to
zero or preset to nine by applying appropriate logic level on
the R
01
, R
02
, R
91
and R
92
inputs. Also, a separate flip-flop
on the A-bit enables the user to operate it as a divide-by-2,
5 or 10 frequency counter. The 4-bit binary counter can be
reset to zero by applying high logic level on inputs R
01
and
R
02
, and a separate flip-flop on the A-bit enables the user
to operate it as a divide-by-2, -8, or -16 divider. Counting
occurs on the negative going edge of the input pulse.
All inputs are protected against static discharge damage.
Features
s
Wide supply voltage range:
3V to 15V
s
Guaranteed noise margin: 1V
s
High noise immunity: 0.45 V
CC
(typ.)
s
Low power compatibility:
Fan out of 2 TTL driving 74L
s
The MM74C93 follows the MM74L93 Pinout
Ordering Code:
Order Number
MM74C90N
MM74C93N
Package Number
N14A
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagrams
MM74C90
MM74C93
Top View
Top View
© 2002 Fairchild Semiconductor Corporation
DS005889
www.fairchildsemi.com

MM74C93 Related Products

MM74C93 MM74C90_02 MM74C90N MM74C90
Description CMOS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14 CMOS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14 CMOS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14 CMOS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14
Number of functions 2 2 2 2
Number of terminals 14 14 14 14
Maximum operating temperature 85 Cel 85 Cel 125 °C 85 Cel
Minimum operating temperature -40 Cel -40 Cel -55 °C -40 Cel
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
Terminal location DUAL DUAL DUAL DUAL
Temperature level INDUSTRIAL INDUSTRIAL MILITARY INDUSTRIAL
series CMOS CMOS CMOS CMOS
Counting direction UP UP UP UP
Operating mode ASYN ASYN ASYNCHRONOUS ASYN
Number of digits 3 3 3 3
Trigger type NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
Maximum supply/operating voltage 15 V 15 V - 15 V
Minimum supply/operating voltage 3 V 3 V - 3 V
Rated supply voltage 5 V 5 V - 5 V
Processing package description PLASTIC, DIP-14 PLASTIC, DIP-14 - PLASTIC, DIP-14
state TRANSFERRED TRANSFERRED - TRANSFERRED
Craftsmanship CMOS CMOS - CMOS
packaging shape RECTANGULAR RECTANGULAR - RECTANGULAR
Package Size IN-LINE IN-LINE - IN-LINE
Terminal spacing 2.54 mm 2.54 mm - 2.54 mm
Packaging Materials PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY
Load preset input ASYN PRESET ASYN PRESET - ASYN PRESET
Logic IC type DECADE COUNTER DECADE COUNTER - DECADE COUNTER
propagation delay TPD 400 ns 400 ns - 400 ns
Max-Min frequency 2 MHz 2 MHz - 2 MHz
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