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EPA572-20A

Description
7 Pin Single-in-Line Package Passive Delay Lines
Categorylogic    logic   
File Size9KB,1 Pages
ManufacturerPCA Electronics Inc.
Websitehttp://www.pca.com/
Download Datasheet Parametric Compare View All

EPA572-20A Overview

7 Pin Single-in-Line Package Passive Delay Lines

EPA572-20A Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPCA Electronics Inc.
Parts packaging codeSIP
package instructionSIP-7
Contacts7
Reach Compliance Codecompliant
Other featuresMAX RISE TIME CAPTURED
Input frequency maximum value (fmax)10 MHz
JESD-30 codeR-XSIP-T7
JESD-609 codee0
Logic integrated circuit typePASSIVE DELAY LINE
Humidity sensitivity level3
Number of functions1
Number of taps/steps5
Number of terminals7
Maximum operating temperature70 °C
Minimum operating temperature
Output impedance nominal value (Z0)50 Ω
Output polarityTRUE
Package body materialUNSPECIFIED
encapsulated codeSIP
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
programmable delay lineNO
Certification statusNot Qualified
Maximum seat height6.35 mm
surface mountNO
technologyHYBRID
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationSINGLE
Maximum time at peak reflow temperatureNOT SPECIFIED
Total delay nominal (td)20 ns
Base Number Matches1
7 Pin Single-in-Line Package Passive Delay Lines
Zo
OHMS
±10%
DELAY
nS ±5%
or
±2 nS†
5
10
20
30
40
50
60
70
80
90
100
TAP
DELAYS
±5% or
±2 nS†
1
2
4
6
8
10
12
14
16
18
20
RISE
TIME
nS
Max.
2
3
6
9
12
15
18
22
24
27
28
DCR
OHMS
Max.
PCA
PART
NUMBER
Zo
DELAY
OHMS nS ±5%
±10%
or
±2 nS †
100
100
100
100
100
100
100
100
100
100
100
5
10
20
30
40
50
60
70
80
90
100
TAP
DELAYS
±5% or
±2 nS†
1
2
4
6
8
10
12
14
16
18
20
RISE
TIME
nS
Max.
2
3.3
6
9
11
14
17
21
23
25
28
DCR
OHMS
Max.
PCA
PART
NUMBER
50
50
50
50
50
50
50
50
50
50
50
0.3
0.5
0.8
1.2
1.8
2.3
2.5
3.5
4.2
4.5
5.2
EPA572-5A
EPA572-10A
EPA572-20A
EPA572-30A
EPA572-40A
EPA572-50A
EPA572-60A
EPA572-70A
EPA572-80A
EPA572-90A
EPA572-100A
0.5
1.0
1.5
2.5
4.0
5.0
5.5
6.0
6.5
7.0
7.5
EPA572-5B
EPA572-10B
EPA572-20B
EPA572-30B
EPA572-40B
EPA572-50B
EPA572-60B
EPA572-70B
EPA572-80B
EPA572-90B
EPA572-100B
†Whichever
is greater.
DC Electrical Characteristics
Distortion
Temperature Coefficient of Delay
Insulation Resistance @ 100 Vdc
Dielectric Strength
Min
Max
±10
100
Unit
%
PPM/°C
Meg Ohms
Vdc
Schematic
6
IN
5
4
3
2
1
OUT
1K
100
7
GROUND
Recommended Operating
Conditions
PW*
D*
TA
Pulse Width % of Total Delay
Duty Cycle
Operating Free Air Temperature
Package Dimensions
Min
200
0
40
70
Max
Unit
%
%
°C
.250 Max.
.195
Max
.022
Min.
.130 Min.
.022
Typ.
.800 Max.
PCA
EPA572-5A
Date Code
*These two values are inter-dependent.
.010
Typ.
C
L
.100 Typ.
Input Pulse Test Conditions @ 25°C
VIN
PW
TRI
PRR
Pulse Input Voltage
Pulse Width % of Total Delay
Input Rise Time (10 - 90%)
Pulse Repetition Rate @ Td
150 nS
Pulse Repetition Rate @ Td > 150 nS
3 Volts
300 %
2.0 nS
1.0 MHz
300 KHz
DSA572A/B Rev. B 2/5/96
QAF-CSO1 Rev. B 8/25/94
Unless Otherwise Noted Dimensions in Inches
Tolerances:
Fractional = ± 1/32
.XX = ± .030
.XXX = ± .010
ELECTRONICS
INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
FAX: (818) 894-5791

EPA572-20A Related Products

EPA572-20A EPA572-10A EPA572-5A EPA572-30A
Description 7 Pin Single-in-Line Package Passive Delay Lines 7 Pin Single-in-Line Package Passive Delay Lines 7 Pin Single-in-Line Package Passive Delay Lines 7 Pin Single-in-Line Package Passive Delay Lines
Is it lead-free? Contains lead Contains lead Contains lead Contains lead
Is it Rohs certified? incompatible incompatible incompatible incompatible
Maker PCA Electronics Inc. PCA Electronics Inc. PCA Electronics Inc. PCA Electronics Inc.
Parts packaging code SIP SIP SIP SIP
package instruction SIP-7 SIP-7 SIP-7 SIP-7
Contacts 7 7 7 7
Reach Compliance Code compliant compli compli compli
Other features MAX RISE TIME CAPTURED MAX RISE TIME CAPTURED MAX RISE TIME CAPTURED MAX RISE TIME CAPTURED
Input frequency maximum value (fmax) 10 MHz 20 MHz 40 MHz 6.66667 MHz
JESD-30 code R-XSIP-T7 R-XSIP-T7 R-XSIP-T7 R-XSIP-T7
JESD-609 code e0 e0 e0 e0
Logic integrated circuit type PASSIVE DELAY LINE PASSIVE DELAY LINE PASSIVE DELAY LINE PASSIVE DELAY LINE
Humidity sensitivity level 3 3 3 3
Number of functions 1 1 1 1
Number of taps/steps 5 5 5 5
Number of terminals 7 7 7 7
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C
Output impedance nominal value (Z0) 50 Ω 50 Ω 50 Ω 50 Ω
Output polarity TRUE TRUE TRUE TRUE
Package body material UNSPECIFIED UNSPECIFIED UNSPECIFIED UNSPECIFIED
encapsulated code SIP SIP SIP SIP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE IN-LINE IN-LINE IN-LINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
programmable delay line NO NO NO NO
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 6.35 mm 6.35 mm 6.35 mm 6.35 mm
surface mount NO NO NO NO
technology HYBRID HYBRID HYBRID HYBRID
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface TIN LEAD TIN LEAD TIN LEAD TIN LEAD
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
Terminal pitch 2.54 mm 2.54 mm 2.54 mm 2.54 mm
Terminal location SINGLE SINGLE SINGLE SINGLE
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Total delay nominal (td) 20 ns 10 ns 5 ns 30 ns

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