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TDA7500A

Description
DIGITAL AM/FM SIGNAL PROCESSOR
CategoryOther integrated circuit (IC)    Consumption circuit   
File Size416KB,40 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
Download Datasheet Parametric View All

TDA7500A Overview

DIGITAL AM/FM SIGNAL PROCESSOR

TDA7500A Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Parts packaging codeQFP
package instructionTQFP-100
Contacts100
Reach Compliance Codecompli
Commercial integrated circuit typesCONSUMER CIRCUIT
JESD-30 codeS-PQFP-G100
JESD-609 codee4
length14 mm
Number of functions1
Number of terminals100
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP100,.63SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum slew rate490 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
Base Number Matches1
TDA7500A
DIGITAL AM/FM SIGNAL PROCESSOR
s
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s
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P
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BLOCK DIAGRAM
analog in
Σ∆
Σ∆
Σ∆
Σ∆
ADC-ref
FULL SOFTWARE FLEXIBILITY WITH TWO
24X24 BIT DSP CORES
SOFTWARE AM/FM, AUDIO AND SOUND-
PROCESSING
HARDWARE RDS FILTER, DEMODULATOR
& DECODER
INTEGRATED CODEC (4ADCs, 6DACs)
IIC AND SPI CONTROL INTERFACES
SPI DEDICATED TO DISPLAY MICRO
6 CHANNEL SERIAL AUDIO INTERFACE
(SAI)
SPDIF RECEIVER WITH SAMPLE RATE
CONVERTER
EXTERNAL MEMORY INTERFACE (EMI)
DOUBLE DEBUG INTERFACE
ON-CHIP PLL
5V-TOLERANT 3V I/O INTERFACE
12x2 MULTIFUNCTION GENERAL PURPOSE
I/O PORTS
TQFP100 (with slug down)
ORDERING NUMBER: TDA7500A
DESCRIPTION
b
O
The TDA7500A is an integrated circuit implementing
a fully digital, integrated and advanced solution to
perform the signal processing in front of the power
amplifier and behind the AM/FM tuner or any other
audio source. The chip integrates two 45 MIPs DSP
cores: one for stereo decoding, noise blanking, weak
signal processing and multipath detection and one for
sound processing, Dolby B, echo and noise cancel-
ling for the telephone.
so
te
le
ro
P
uc
d
s)
t(
P
e
od
r
s)
t(
uc
analog audio out
Decimation
Filter
Decimation
Filter
PLL Clock
Generator
SC
Filter
SC
Filter
SC
Filter
SC
Filter
SC
Filter
SC
Filter
DAC-ref
Noise
Shaper
Noise
Shaper
Noise
Shaper
ADCVDD
ADCGND
AVDD
AGND
Oversampl. Oversampl. Oversampl.
Filter
Filter
Filter
Grp & blk
sync., error
correction
IIC / SPI 1
SPI 2
SAI Transmitter
SRAM 4Mx8
DRAM 128kx4
RDS
Filter
Demod.
SPI
CLK in
Error corr. RDS blocks
or RDS clk, dat, qual
RDS
RDS bit/blk Int.
4
RDS SPI
Crystal
Oscillator
4
4
3
2
8+3
17
6 Ch. Audio Bus
2
receive bit&word clk
digital audio in
10 word SPI 1
receive stack
λ
P control
Display
λ
P
6 Channel
Audio Bus
SPDIF audio in
SAI 6ch.
Receiver
SPDIF 2ch.
Interface
2ch Sample
Rate
Converter
External Memory Interface
DSP1 Orpheus Core
including 12 GPIO´s
DSP0 Orpheus Core
X Ram 1024
Y Ram 1024
P Ram 2048
P Rom 256
Xchg
Interf.
including 12 GPIO´s
Int
Reset
4
4
2
Test
4
VDD
GND
Dolby B
FM processing,
AM processing,
Traffic memorization
4
Debug Interface
X Ram 1024
Y Ram 1024
P Ram 5632
P Rom 512
Audio processing,
Sound processing,
Noise & Echo Canc.
Debug Interface
December 2001
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