EEWORLDEEWORLDEEWORLD

Part Number

Search

DDU18-48MC3

Description
Active Delay Line, 1-Func, 8-Tap, True Output, ECL, SMD-24
Categorylogic    logic   
File Size43KB,4 Pages
ManufacturerData Delay Devices
Download Datasheet Parametric View All

DDU18-48MC3 Overview

Active Delay Line, 1-Func, 8-Tap, True Output, ECL, SMD-24

DDU18-48MC3 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeSOIC
package instructionSOP,
Contacts24
Reach Compliance Codecompliant
JESD-30 codeR-XDSO-G24
length32.512 mm
Logic integrated circuit typeACTIVE DELAY LINE
Number of functions1
Number of taps/steps8
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature
Output characteristicsOPEN-EMITTER
Output polarityTRUE
Package body materialUNSPECIFIED
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
programmable delay lineNO
Certification statusNot Qualified
Maximum seat height7.112 mm
surface mountYES
technologyECL
Temperature levelOTHER
Terminal formGULL WING
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Total delay nominal (td)48 ns
Base Number Matches1
DDU12H
5-TAP, ECL-INTERFACED
FIXED DELAY LINE
(SERIES DDU12H)
FEATURES
GND
1
3
4
5
32
31
30
29
data
3
®
delay
devices,
inc.
PACKAGES
GND
T1
T3
T5
T2
T4
IN
Ten equally spaced outputs
Fits in 300 mil 32-pin DIP socket
Input & outputs fully 10KH-ECL interfaced & buffered
VEE
GND
T2
T4
8
9
11
12
24
23
22
21
GND
T6
T8
T10
GND
T2
T4
IN
N/C
VEE
GND
N/C
N/C
T7
T8
VEE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
T1
T3
T5
N/C
N/C
GND
N/C
N/C
T6
T8
T10
DDU12H-xx DIP
DDU12H-xxM Military DIP
VEE
16
DDU12H-xxC3 SMD
DDU12H-xxMC3 Mil SMD
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The DDU12H-series device is a 10-tap digitally buffered delay line. The
IN
Signal Input
signal input (IN) is reproduced at the outputs (T1-T10), shifted in time by
T1-T10 Tap Outputs
an amount determined by the device dash number (See Table). For dash
VEE
-5 Volts
numbers less than 20, the total delay of the line is measured from T1 to
GND Ground
T10. The nominal tap-to-tap delay increment is given by one-ninth of the
total delay, and the inherent delay from IN to T1 is nominally 1.5ns. For dash numbers greater than or
equal to 20, the total delay of the line is measured from IN to T10. The nominal tap-to-tap delay increment
is given by one-tenth of this number.
SERIES SPECIFICATIONS
Minimum input pulse width:
10% of total delay
Output rise time:
2ns typical
Supply voltage:
-5VDC
±
5%
Power dissipation:
400mw typical (no load)
Operating temperature:
-30° to 85° C
Temp. coefficient of total delay:
100 PPM/°C
1.5ns
10%
10%
10%
10%
10%
10%
10%
10%
10%
DASH NUMBER SPECIFICATIONS
Part
Number
DDU12H-10
DDU12H-20
DDU12H-25
DDU12H-40
DDU12H-50
DDU12H-75
DDU12H-100
DDU12H-150
DDU12H-200
DDU12H-250
DDU12H-300
DDU12H-400
DDU12H-500
DDU12H-750
DDU12H-1000
DDU12H-1500
Total
Delay (ns)
9
±
1.0 *
20
±
2.0
25
±
2.0
40
±
2.0
50
±
2.5
75
±
4.0
100
±
5.0
150
±
7.5
200
±
10.0
250
±
12.5
300
±
15.0
400
±
20.0
500
±
25.0
750
±
37.5
1000
±
50.0
1500
±
75.0
Delay Per
Tap (ns)
1.0
±
0.3
2.0
±
0.4
2.5
±
0.4
4.0
±
0.5
5.0
±
1.0
7.5
±
1.5
10.0
±
2.0
15.0
±
2.0
20.0
±
2.0
25.0
±
2.0
30.0
±
2.0
40.0
±
2.0
50.0
±
2.5
75.0
±
4.0
100.0
±
5.0
150.0
±
7.0
VCC IN
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 GND
Functional diagram for dash numbers < 20
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
VCC IN
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 GND
* Total delay is referenced to first tap output
Input to first tap = 1.5ns
±
1ns
NOTE: Any dash number between 10 and 1500
not shown is also available.
Functional diagram for dash numbers >= 20
©
1997 Data Delay Devices
Doc #97036
12/11/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
What are the benefits of DSP program architecture?
[color=#555555][font="][size=4]I learned DSP C2000 series and read a lot of examples and documents. I found that the program architecture is basically the following structure: [/size][/font][/color] [...
Jacktang DSP and ARM Processors
Expose my indenture (answers will be announced after the 11th floor)
As the title suggests, dear audience friends, where is your enthusiasm??? Take your courage and push this post up as soon as possible!!! [[i] This post was last edited by jxb01033016 on 2010-3-25 16:2...
jxb01033016 Talking about work
How is the development of purely domestic MCU? Pingtouge RISC-V chip development board review
Video source | HACK Lab...
未来开发者 XuanTie RISC-V Activity Zone
About IO interrupt debounce problem~
[color=#000000]I've been playing with the msp430f149 development board recently. I used it to build an infrared detection circuit (a ready-made module) to detect the speed of liquid titration~~~[/colo...
liuchang--- Microcontroller MCU
Blame others
It means that when encountering setbacks or problems, one just complains and blames others. King Xiang wanted to cross the Wu River to the east. The headman of the Wu River moored his boat and said to...
PowerAnts Talking
I have a question about the normalization calculation of multi-order low-pass filters. Thank you!
In the above figure, the filter design is calculated according to the parameters of the normalized table on the right to determine the values of resistance and capacitance.However, the frequency in th...
sxbo88 Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1133  2843  287  888  486  23  58  6  18  10 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号