PEEL18CV8LS-15 datasheet, PDF - EEWORLD Datasheet

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PEEL18CV8LS-15: DescriptionEE PLD, 15ns, PAL-Type, CMOS, PDSO20, SOIC-20; CategoryProgrammable logic devices Programmable logic; File Size231KB，3 Pages; ManufacturerIntegrated Circuit Systems（IDT ）

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PEEL18CV8LS-15 Overview

EE PLD, 15ns, PAL-Type, CMOS, PDSO20, SOIC-20

PEEL18CV8LS-15 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	SOP, SOP20,.4
Contacts	20
Reach Compliance Code	unknown
Other features	8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE
maximum clock frequency	41.6 MHz
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	12.8 mm
Dedicated input times	9
Number of I/O lines	8
Number of entries	18
Output times	8
Number of product terms	74
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
organize	9 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	5 V
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.5 mm
Base Number Matches	1

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PEEL18CV8LS-15 Related Products

	PEEL18CV8LS-15	PEEL18CV8LP-15	PEEL18CV8LJ-15
Description	EE PLD, 15ns, PAL-Type, CMOS, PDSO20, SOIC-20	EE PLD, 15ns, PAL-Type, CMOS, PDIP20, 0.300 INCH, PLASTIC, DIP-20	EE PLD, 15ns, PAL-Type, CMOS, PQCC20, PLASTIC, LCC-20
Is it Rohs certified?	incompatible	incompatible	incompatible
Parts packaging code	SOIC	DIP	QLCC
package instruction	SOP, SOP20,.4	DIP, DIP20,.3	QCCJ, LDCC20,.4SQ
Contacts	20	20	20
Reach Compliance Code	unknown	unknown	unknown
Other features	8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE	PAL-TYPE	PAL-TYPE
maximum clock frequency	41.6 MHz	41.6 MHz	41.6 MHz
JESD-30 code	R-PDSO-G20	R-PDIP-T20	S-PQCC-J20
JESD-609 code	e0	e0	e0
length	12.8 mm	26.162 mm	8.9662 mm
Dedicated input times	9	9	9
Number of I/O lines	8	8	8
Number of entries	18	18	18
Output times	8	8	8
Number of product terms	74	74	74
Number of terminals	20	20	20
Maximum operating temperature	70 °C	70 °C	70 °C
organize	9 DEDICATED INPUTS, 8 I/O	9 DEDICATED INPUTS, 8 I/O	9 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	DIP	QCCJ
Encapsulate equivalent code	SOP20,.4	DIP20,.3	LDCC20,.4SQ
Package shape	RECTANGULAR	RECTANGULAR	SQUARE
Package form	SMALL OUTLINE	IN-LINE	CHIP CARRIER
power supply	5 V	5 V	5 V
Programmable logic type	EE PLD	EE PLD	EE PLD
propagation delay	15 ns	15 ns	15 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V
surface mount	YES	NO	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	THROUGH-HOLE	J BEND
Terminal pitch	1.27 mm	2.54 mm	1.27 mm
Terminal location	DUAL	DUAL	QUAD
width	7.5 mm	7.62 mm	8.9662 mm
Base Number Matches	1	1	1
Maximum seat height	2.65 mm	-	4.369 mm

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