74VHCT74A Dual D-Type Flip-Flop with Preset and Clear
July 1997
Revised April 1999
74VHCT74A
Dual D-Type Flip-Flop with Preset and Clear
General Description
The VHCT74A is an advanced high speed CMOS Dual D-
Type Flip-Flop fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The signal level applied to the D INPUT
is transferred to the Q OUTPUT during the positive going
transition of the CK pulse. CLR and PR are independent of
the CK and are accomplished by setting the appropriate
input LOW.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with V
CC
=
0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup.
Features
s
High speed: f
MAX
=
160 MHz (typ) at T
A
=
25°C
s
High noise immunity: V
IH
=
2.0V, V
IL
=
0.8V
s
Power down protection is provided on all inputs and
outputs
s
Low power dissipation:
I
CC
=
2
µA
(max) at T
A
=
25°C
s
Pin and function compatible with 74HCT74
Ordering Code:
Order Number
74VHCT74AM
74VHCT74ASJ
74VHCT74AMTC
74VHCT74AN
Package Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
D
1
, D
2
CK
1
, CK
2
CLR
1
, CLR
2
PR
1
, PR
2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Preset Inputs
Outputs
Truth Table
Inputs
CLR
L
H
L
H
H
H
PR
H
L
L
H
H
H
D
X
X
X
L
H
X
CK
X
X
Outputs
Function
Q
L
H
H
L
H
Q
n
Q
H
L
H
H
L
Q
n
No
Change
Clear
Preset
X
© 1999 Fairchild Semiconductor Corporation
DS500026.prf
www.fairchildsemi.com
74VHCT74A
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
(Note 2)
(Note 3)
Input Diode Current (I
IK
)
Output Diode Current (I
OK
)
(Note 4)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
Soldering (10 seconds)
260°C
±20
mA
±25
mA
±50
mA
−65°C
to
+150°C
−0.5V
to V
CC
+
0.5V
−0.5V
to 7.0V
−20
mA
−0.5V
to
+7.0V
−0.5V
to
+7.0V
Recommended Operating
Conditions
(Note 5)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
(Note 2)
(Note 3)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
5.0V
±
0.5V
0 ns/V
∼
20 ns/V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading varai-
bles. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2:
HIGH or LOW state. I
OUT
absolute maximum rating must be
observed.
Note 3:
V
CC
=
0V.
Note 4:
V
OUT
<
GND, V
OUT
>
V
CC
.(Outputs Active)
Note 5:
Unused inputs must be held HIGH or LOW. They may not float.
4.5V to 5.5V
0V to
+5.5V
0V to V
CC
0V to 5.5V
−40°C
to
+85°C
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
I
CC
I
CCT
I
OFF
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
Input Leakage Current
Quiescent Supply Current
Maximum I
CC
/Input
Output Leakage Current
(Power Down State)
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
4.5
4.5
4.5
0–5.5
5.5
5.5
0.0
4.40
3.94
0.0
0.1
0.36
±0.1
2.0
1.35
+0.5
4.50
T
A
=
25°C
Min
2.0
2.0
0.8
0.8
4.40
3.80
0.1
0.44
±1.0
20.0
1.50
+5.0
Typ
Max
T
A
= −40°C
to
+85°C
Min
2.0
2.0
0.8
0.8
Max
Units
V
V
V
V
µA
µA
mA
µA
V
IN
=
V
IH
I
OH
= −50 µA
Conditions
or V
IL
I
OH
= −8
mA
V
IN
=
V
IH
I
OL
=
50
µA
or V
IL
I
OL
=
8 mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
V
IN
=
3.4V
Other Inputs
=
V
CC
or GND
V
OUT
=
5.5V
www.fairchildsemi.com
2
74VHCT74A
AC Electrical Characteristics
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
C
IN
C
PD
Parameter
Maximum Clock
Frequency
Propagation Delay Time
(CK-Q, Q)
Propagation Delay time
(CLR, PR -Q, Q)
Input Capacitance
Power Dissipation Capacitance
V
CC
(V)
(Note 6)
5.0
5.0
5.0
5.0
5.0
5.0
T
A
=
25°C
Min
100
80
Typ
160
140
5.8
6.3
7.6
8.1
4
24
7.8
8.8
10.4
11.4
10
Max
T
A
= −40°C
to
+85°C
Min
80
65
1.0
1.0
1.0
1.0
9.0
10.0
12.0
13.0
10
Max
Units
Conditions
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
C
L
=
15 pF
C
L
=
50 pF
V
CC
=
Open
(Note 7)
MHz
ns
ns
pF
pF
Note 6:
V
CC
is 5.0
±
0.5V
Note 7:
C
PD
is defined as the value of internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr)
=
C
PD
×
V
CC
×
f
IN
+
I
CC
/2 (per flip-flop).
AC Operating Requirements
Symbol
t
W
(L)
t
W
(H)
t
W
(L)
t
S
t
H
t
REM
Minimum Pulse Width
(CLR, PR)
Minimum Setup Time
Minimum Hold Time
Minimum Removal Time
(CLR, PR)
Parameter
Minimum Pulse Width (CK)
V
CC
(V)
5.0
±
0.5
5.0
±
0.5
5.0
±
0.5
5.0
±
0.5
5.0
±
0.5
T
A
=
25°C
Typ
T
A
= −40°C
to
+85°C
Guaranteed Minimum
5.0
5.0
5.0
0
3.5
5.0
5.0
5.0
0
3.5
ns
ns
ns
ns
ns
Units
3
www.fairchildsemi.com
74VHCT74A
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com
4
京公网安备 11010802033920号
EEWORLD
