ICS95V857YKLFT datasheet, PDF - EEWORLD Datasheet

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ICS95V857YKLFT: DescriptionPLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), MLF-40; Categorylogic logic; File Size189KB，13 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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ICS95V857YKLFT Overview

PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), MLF-40

ICS95V857YKLFT Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	DFN
package instruction	VQCCN,
Contacts	40
Manufacturer packaging code	MLF
Reach Compliance Code	compliant
Input adjustment	DIFFERENTIAL
JESD-30 code	S-XQCC-N40
JESD-609 code	e3
length	6 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	40
Actual output times	10
Maximum operating temperature	85 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	VQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.03 ns
Maximum seat height	0.9 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	OTHER
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	6 mm
minfmax	170 MHz
Base Number Matches	1

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Integrated

Circuit

Systems, Inc.

ICS95V857-XXX

Preliminary Product Preview

2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)

Recommended Application:

DDR Memory Modules / Zero Delay Board Fan Out

Product Description/Features:

• Low skew, low jitter PLL clock driver

• 1 to 10 differential clock distribution (SSTL2)

• Feedback pins for input to output synchronization

• PD# for power management

• Spread Spectrum-tolerant inputs

• Auto PD when input signal removed

• Choice of static phase offset available,

for easy board tuning;

-XXX = device pattern number for options listed

below.

ICS95V857 .............

0ps

ICS95V857-130 ..

+50ps

Specifications:

• Meets or exceeds JEDEC standard #82-1 for

registered DDR clock driver.

• Meets or exceeds proposed DDR1-400 specifications

• Covers all DDR1 speed grades

Switching Characteristics:

• CYCLE - CYCLE jitter (>100MHz):<50ps

• OUTPUT - OUTPUT skew: <30ps

• Output Rise and Fall Time: 650ps - 950ps

• DUTY CYCLE: 49.5% - 50.5%

Pin Configuration

GND

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

CLKC2

CLKT2

VDD

CLK_INT

CLK_INC

VDD

AVDD

AGND

GND

CLKC3

CLKT3

VDD

CLKT4

CLKC4

GND

CLKC5

CLKT5

VDD

CLKT6

CLKC6

GND

CLKC7

CLKT7

VDD

PD#

FB_INT

FB_INC

VDD

FB_OUTC

FB_OUTT

GND

CLKC8

CLKT8

VDD

CLKT9

CLKC9

GND

48-Pin TSSOP/TVSOP

6.10 mm Body, 0.50 mm Pitch = TSSOP

4.40 mm Body, 0.40 mm Pitch = TVSOP

Block Diagram

FB_OUTT

FB_OUTC

CLKT0

CLKC0

CLKT1

CLKC1

Functionality

INPUTS

AVDD PD#

GND

2.5V

(nom)

2.5V

(nom)

2.5V

(nom)

2.5V

(nom)

2.5V

(nom)

CLK_INT

<20MHz)

(1)

OUTPUTS

PLL State

CLK_INC CLKT CLKC FB_OUTT FB_OUTC

Bypassed/off

off

Control

PD#

Logic

ICS95V857-XXX

CLKT2

CLKC2

CLKT3

CLKC3

CLKT4

CLKC4

FB_INT

FB_INC

CLK_INC

CLK_INT

CLKT5

CLKC5

PLL

CLKT6

CLKC6

CLKT7

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

0674I—03/28/03

PRODUCT PREVIEW

documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are

subject to change without notice.

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Description	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), MLF-40	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), MLF-40	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.173 INCH, TSSOP-48	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.173 INCH, TSSOP-48	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240 INCH, TSSOP-48	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240 INCH, TSSOP-48	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240 INCH, TSSOP-48	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240 INCH, TSSOP-48	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PBGA56, BGA-56	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PBGA56, BGA-56
Is it lead-free?	Lead free	Contains lead	Contains lead	Lead free	Lead free	Lead free	Contains lead	Contains lead	Contains lead	Lead free
Is it Rohs certified?	conform to	incompatible	incompatible	conform to	conform to	conform to	incompatible	incompatible	incompatible	conform to
Parts packaging code	DFN	DFN	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	BGA	BGA
package instruction	VQCCN,	VQCCN,	TSSOP,	TSSOP,	TSSOP,	TSSOP,	TSSOP,	TSSOP,	VFBGA,	VFBGA,
Contacts	40	40	48	48	48	48	48	48	56	56
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
Input adjustment	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL
JESD-30 code	S-XQCC-N40	S-XQCC-N40	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PBGA-B56	R-PBGA-B56
JESD-609 code	e3	e0	e0	e3	e3	e3	e0	e0	e0	e3
length	6 mm	6 mm	9.7 mm	9.7 mm	12.5 mm	12.5 mm	12.5 mm	12.5 mm	7 mm	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of terminals	40	40	48	48	48	48	48	48	56	56
Actual output times	10	10	10	10	10	10	10	10	10	10
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VQCCN	VQCCN	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	VFBGA	VFBGA
Package shape	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER, VERY THIN PROFILE	CHIP CARRIER, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	NOT SPECIFIED	NOT SPECIFIED	260	260	260	240	240	NOT SPECIFIED	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.03 ns	0.03 ns	0.03 ns	0.03 ns	0.03 ns	0.03 ns	0.03 ns	0.03 ns	0.03 ns	0.03 ns
Maximum seat height	0.9 mm	0.9 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1 mm	1 mm
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal surface	Matte Tin (Sn)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Matte Tin (Sn)	Matte Tin (Sn)	MATTE TIN	Tin/Lead (Sn/Pb)	TIN LEAD	Tin/Lead (Sn/Pb)	Matte Tin (Sn)
Terminal form	NO LEAD	NO LEAD	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	BALL	BALL
Terminal pitch	0.5 mm	0.5 mm	0.4 mm	0.4 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	NOT SPECIFIED	NOT SPECIFIED	30	30	30	20	20	NOT SPECIFIED	30
width	6 mm	6 mm	4.4 mm	4.4 mm	6.1 mm	6.1 mm	6.1 mm	6.1 mm	4.5 mm	4.5 mm
minfmax	170 MHz	170 MHz	170 MHz	170 MHz	170 MHz	170 MHz	170 MHz	170 MHz	170 MHz	170 MHz
Maker	-	-	-	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)

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