Preliminary
7
Typical Applications
• W-CDMA Systems
RF2679
W-CDMA RECEIVE AGC AND DEMODULATOR
Product Description
The RF2679 is an integrated complete IF AGC amplifier
and Quadrature Demodulator designed for the receive
section of W-CDMA applications. It is designed to amplify
received IF signals, while providing 60dB of gain control
range, a total of 90dB gain, and demodulate to baseband
I and Q signals. This circuit is designed as part of
RFMD’s single-mode W-CDMA Chipset, which also
includes the RF2678 W-CDMA Transmit Modulator and IF
AGC. The IC is manufactured on an advanced 25GHz F
T
Silicon Bi-CMOS process, and is packaged in a
4mmx4mm LPCC-24.
4.00
+0.20
0.90
+0.10
4.00
+0.20
2.80
+0.05 sq
7
QUADRATURE
DEMODULATORS
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
2.50
sq
0.40
+0.05
0.500
+0.025
Optimum Technology Matching® Applied
Package Style: LPCC-24
!
Si Bi-CMOS
BG OUT
24
GC 1
DEC 2
CDMA IN+ 3
CDMA IN- 4
VCC1 5
VCC2 6
7
VCC3
Si BJT
GaAs HBT
SiGe HBT
ENABLE
CALEN
GaAs MESFET
Si CMOS
QDCFB
Features
• Digitally Controlled Power Down Mode
• 2.7V to 3.3V Operation
• Digital LO Quadrature Divide-by-4
• IF AGC Amp with 70dB Gain Control
• 85dB Maximum Voltage Gain
FL+
22
23
21
FL-
20
19
18 IDCFB
Band Gap
Reference
Gain
Control
BB Filter
17 I OUT+
16 I OUT-
BB Filter
15 GND2
14 Q OUT+
13 Q OUT-
10
GND1
11
VCC4
12
FCLK
Quad.
÷4
8
LO+
9
LO-
Ordering Information
RF2679
RF2679 PCBA
W-CDMA Receive AGC and Demodulator
Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc.
7625 Thorndike Road
Greensboro, NC 27409, USA
Rev A0 000825
7-39
RF2679
Absolute Maximum Ratings
Parameter
Supply Voltage
Power Down Voltage (V
PD
)
Input RF Power
Ambient Operating Temperature
Storage Temperature
Preliminary
Rating
-0.5 to +5
-0.5 to V
CC
+0.7
+3
-40 to +85
-40 to +150
Unit
V
DC
V
DC
dBm
°C
°C
Caution!
ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Parameter
Overall (Cascaded)
Maximum Gain
Minimum Gain
Gain Variation vs. V
CC
and T
Input IP3
Specification
Min.
Typ.
Max.
Unit
Condition
T=25 °C, V
CC
=3.0V, Z
LOAD
≅60kΩ,
LO=760MHz @400mV
PP
,
IF Freq=191MHz, Z
S
=500Ω
V
GC
=2.4V, Balanced
V
GC
=0.3V, Balanced
V
CC
=2.7V to 3.3V and T=-30°C to +85°C
Maximum Gain
Minimum Gain
Maximum Gain
Minimum Gain
W-CDMA, Balanced
W-CDMA, Single Ended
+85
+15
-3
-50
-4
5
45
190
2400
1200
2.5
0.2
1
+3
7
QUADRATURE
DEMODULATORS
Noise Figure
IF Input Frequency Range
IF Input Impedance
I/Q Frequency Range
I/Q Amplitude Balance
I/Q Phase Balance
Max I/Q Output Voltage
I/Q DC Output
I/Q DC Offset
Filter
LO Input Frequency Range
LO Input Level
LO Input Impedance
2040
1020
2760
1380
5
1
V
CC
-1.3
5
f
C
=2.5MHz+
-250kHz
760
60 to 600
800
400
3.0
14.5
dB
dB
dB
dBm
dBm
dB
dB
MHz
Ω
Ω
MHz
dB
deg
V
PP
V
DC
mV
DC
20
Balanced, maximum output level,
Z
LOAD
≅60kΩ
Common Mode
I OUT+ to I OUT-; QOUT+ to Q OUT-
3rd order Butterworth after autocal
FCLK=19.2MHz@100mVrms
Balanced
Balanced
Single Ended
680
340
2.7
920
460
3.3
10
MHz
mV
PP
Ω
Ω
V
DC
mA
µA
Power Supply
Supply Voltage
Current Consumption
Sleep Mode (ENABLE≤ 0.5V)
7-40
Rev A0 000825
Preliminary
Pin
1
Function
GC
Description
Analog Gain Control for AGC Amplifiers. The valid control range is from
0.3 to 2.4V
DC
. These voltages are valid for ONLY a 68kΩ source
impedance. The gain range for the AGC is 60dB.
RF2679
Interface Schematic
BIAS
21 kΩ
GC
40 kΩ
2
DEC
3
WCDMA IN+
AGC decoupling pin. An external bypass capacitor of 10nF capacitor is
required. The trace length between the pin and the bypass capacitor
should be minimized. The ground side of the bypass capacitor should
connect immediately to ground plane.
W-CDMA Balanced Input pin. This pin is internally DC biased and
should be DC blocked if connected to a device with a DC level present.
For single-ended input operation, one pin is used as an input and the
other W-CDMA input is AC coupled to ground. The balanced input
impedance is 2.4kΩ, while the single-ended input impedance is 1.2kΩ.
CDMA IN+
BIAS
BIAS
1200
Ω
1200
Ω
CDMA IN-
7
Supply voltage for the AGC input stage, band gap and gain control bias
circuitry. This pin may be connected in parallel with pins 6 and 7. It
should be bypassed by a 22nF capacitor. The trace length between the
pin and the bypass capacitor should be minimized. The ground side of
the bypass capacitor should connect immediately to ground plane. The
part is designed to work from a 2.7V to 3.3V supply.
Supply voltage for the bandgap, gain control bias circuitry, and AGC
stages 2 and 3. This pin may be connected in parallel with pins 5 and 7.
It should be bypassed by a 22nF capacitor. The trace length between
the pin and the bypass capacitor should be minimized. The ground side
of the bypass capacitor should connect immediately to ground plane.
The part is designed to work from a 2.7V to 3.3V supply.
Supply voltage for the LO divider and limiting amp. This pin may be
connected in parallel with pins 5 and 6. It should be bypassed by a
22nF capacitor. The trace length between the pin and the bypass
capacitor should be minimized. The ground side of the bypass capaci-
tor should connect immediately to ground plane. The part is designed
to work from a 2.7V to 3.3V supply.
Same as pin 12, except complementary input.
LO Balanced Input pin. This pin is internally DC biased and should be
DC blocked if connected to a device with DC present. For single-ended
input operation, one pin is used as an input and the other LO input is
AC coupled to ground. The frequency of the signal applied to these
pins is internally divided by a factor of 4, hence the carrier frequency for
the modulator becomes one fourth of the applied frequency. The single-
ended input impedance is 400Ω (balanced is 800Ω). The LO input may
be driven single-ended but balanced provides optimum gain and phase
balance.
Ground connection. Keep traces physically short and connect immedi-
ately to ground plane for best performance.
Supply voltage for the baseband stage. This pin should be bypassed by
a 100nF capacitor.
QUADRATURE
DEMODULATORS
B IA S
400
Ω
LO +
4
5
WCDMA IN-
VCC1
Same as pin 4, except complimentary input.
See pin 3.
6
VCC2
7
VCC3
8
9
LO+
LO-
See pin 9.
B IA S
400
Ω
LO -
10
11
GND1
VCC4
Rev A0 000825
7-41
RF2679
Pin
12
13
Function
FCLK
Q OUT-
Description
Reference clock for base band filters.
Preliminary
Interface Schematic
300
Ω
Balanced Baseband Output of Q Mixer. This pin is internally DC biased
and should be DC blocked externally. The output can be used in a sin-
gle-ended configuration by leaving one of the two pins unconnected,
however half the output voltage will be lost.
150
µA
V
CC
V
CC
Q O U T+
Q O U T-
150
µA
14
15
16
17
Q OUT+
GND2
I OUT-
I OUT+
Same as pin 13, except complementary output.
Ground connection for the baseband stage.
Same as pin 17, except complementary output.
Balanced Baseband Output of I Mixer. This pin is internally DC biased
and should be DC blocked externally. The output can be used in a sin-
gle-ended configuration by leaving one of the two pins unconnected,
however half the output voltage will be lost.
See pin 13.
See pin 17.
V
CC
V
CC
I O UT+
150
µA
I O UT-
150
µA
7
QUADRATURE
DEMODULATORS
18
19
20
IDCFB
QDCFB
CALEN
DC feedback capacitor for in-phase channel.
DC feedback capacitor for quadrature channel.
Calibration enable for BB filters. Calibration is performed when CALEN
goes high. The calibration takes approximately 100µs, consumes
0.5mA, and is totally independent of the ENABLE pin. Once calibration
is complete, the calibration word is stored and the calibration circuit is
disabled. If the CALEN pin goes low of V
CC
is disabled, then the cali-
bration word is lost and the IC needs recalibration.
Balanced AGC Output/Demod Input. This balanced node is pinned out
to allow shunt filtering of the AGC output signal as it enters the demod-
ulator. The basic configuration of the filter should consist of a shunt
inductor and shunt capacitor, both connected to the power supply, as
the internal circuitry requires this power supply connection through the
inductor to operate.
21
FL-
FL- FL+
V
CC2
V
CC2
V
CC1
V
CC1
1.2 kΩ
1.2 kΩ
22
23
24
FL+
ENABLE
BG OUT
Same as pin 21, except complementary.
Power Down Control. When logic “high” (≥V
CC
-0.3V), all circuits are
operating; when logic “low” (≤0.5V), all circuits are turned off.
Bandgap Voltage Reference. This voltage, constant over temperature
and supply variation, is used to bias internal circuits. A 10nF external
bypass capacitor is required. The trace length between the pin and the
bypass capacitor should be minimized. The ground side of the bypass
capacitor should connect immediately to ground plane.
See pin 21.
7-42
Rev A0 000825
Preliminary
Pin-Out
ENABLE
BG OUT
QDCFB
CALEN
RF2679
FL+
22
24
GC
DEC
CDMA IN+
CDMA IN-
VCC1
VCC2
1
2
3
4
5
6
7
VCC3
23
21
FL-
20
19
18
17
16
15
14
13
IDCFB
I OUT+
I OUT-
GND2
Q OUT+
Q OUT-
8
LO+
9
LO-
10
GND1
11
VCC4
12
FCLK
7
QUADRATURE
DEMODULATORS
Rev A0 000825
7-43
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