LXP610SE datasheet, PDF - EEWORLD Datasheet

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LXP610SE: DescriptionTelecom Circuit, 1-Func, CMOS, PDSO16, SOIC-16; CategoryWireless rf/communication Telecom circuit; File Size335KB，16 Pages; ManufacturerLevel One

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LXP610SE Overview

Telecom Circuit, 1-Func, CMOS, PDSO16, SOIC-16

LXP610SE Parametric

Parameter Name	Attribute value
Parts packaging code	SOIC
package instruction	,
Contacts	16
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G16
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal location	DUAL
Base Number Matches	1

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DATA SHEET

MARCH 1999

LXP610

Low-Jitter Multi-Rate Clock Adapter (CLAD)

General Description

The LXP610 Multi-Rate Clock Adapter (CLAD) offers

pin-selectable frequency conversion between T1 and E1

rates as well as 8 additional rates from 1.544 MHz to

8.192 MHz. The output clock is frequency-locked to the

input clock. When an input frame sync pulse is provided,

the CLAD phase-locks the input and output clocks

together, and locks the 8 kHz output frame sync pulse to the

input frame sync pulse. The frame sync polarity is also pin-

selectable.

Five different high frequency output clocks are available

for applications which require a higher-than-baud rate

backplane or system clock. The high frequency output

(HFO) clock varies with the input clock frequency.

Level One’s patented locking method enables the CLAD to

perform frequency conversion with no external

components, while generating very little jitter on the output

clock. The conversion is digitally controlled so the output

clock is as accurate as the input clock.

The CLAD is an advanced CMOS device and requires only

a single +5 V power supply.

Revision 1.1

Features

• Translates between 10 different frequencies.

• Generates basic and high frequency output clocks and

frame sync from an input clock and its frame sync.

• High Frequency Output clock for higher-than-baud

rate backplane systems

• Low output jitter meets AT&T Publication 62411 for

1.544 MHz, and ITU Recommendation G.823 for

2.048 MHz

• Digital control of frequency conversion process

• No external components

• Pin-selectable operation mode

• Low-power 5 V only CMOS in 14-pin plastic DIP, 28-

pin PLCC and 16 pin SOIC packages

Applications

• Internal timing system for Channel Banks, Digital

Loop Carriers, Multiplexers, Internal Timing

Generators, etc.

• Conversion between T1/E1 clock rates and higher

frequency backplane rates (T1/E1 converter)

• Special backplane interfaces (e.g. NTI 2.56 MHz)

LXP610 Block Diagram

CLKI

Input

Divider

Analog

Phase-Locked

Loop

Output

Divider

HFO

CLKO

Feedback

Divider

SEL

FSI

Frequency

Converter

Frame Sync

Generator

FSP

FSO

Frequency

Select

Logic

Refer to www.level1.com for most current information.

LXP610SE Related Products

	LXP610SE
Description	Telecom Circuit, 1-Func, CMOS, PDSO16, SOIC-16
Parts packaging code	SOIC
Contacts	16
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G16
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Certification status	Not Qualified
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal location	DUAL
Base Number Matches	1

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