DATASHEET
X5083
CPU Supervisor with 8Kbit SPI EEPROM
This device combines four popular functions, Power-on Reset
Control, Watchdog Timer, Supply Voltage Supervision, and
Block Lock Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET active for a period of time. This
allows the power supply and oscillator to stabilize before the
processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller fails to
restart a timer within a selectable time out interval, the device
activates the RESET signal. The user selects the interval
from three preset values. Once selected, the interval does
not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
CC
trip point. RESET is
asserted until V
CC
returns to the proper operating level and
stabilizes. Five industry standard V
TRIP
thresholds are
available, however, Intersil’s unique circuits allow the threshold
to be reprogrammed to meet custom requirements or to fine-
tune the threshold for applications requiring higher precision.
FN8127
Rev 4.00
November 12, 2015
Features
• Low V
CC
detection and reset assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low V
CC
reset threshold voltage using
special programming sequence
- Reset signal valid to V
CC
= 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lock
™
memory
- Block lock first or last page, any 1/4 or lower 1/2 of
EEPROM array
• Built-in inadvertent write protection
- Write enable latch
- Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
- 16 byte page write mode
- 5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
Pinouts
8 LD TSSOP
ED
RT
PO
RESET
1
8
UP
SCK
S
SI
V
CC
R
2
7
O
X5083
E
V
SS
CS/WDI
L
6
3
AB
WP
4
AIL
5
SO
AV
ER
NG
LO
O
N
Applications
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
8 LD SOIC, 8 LD PDIP
CS/WDI
SO
WP
V
SS
1
8
V
CC
RESET
SCK
SI
2
7
3 X5083 6
4
5
FN8127 Rev 4.00
November 12, 2015
Page 1 of 21
X5083
Typical Application
2.7-5.0V
VCC
X5083
RESET
CS
SCK
SI
SO
WP
VSS
10K
VCC
uC
RESET
SPI
VSS
Block Diagram
POR AND LOW
VOLTAGE RESET
GENERATION
V
CC
V
TRIP
+
-
RESET (X5083)
RESET & WATCHDOG
TIMEBASE
X5083
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
RESET
STANDARD V
TRIP
LEVEL
SUFFIX
4.63V (+/-2.5%)
4.38V (+/-2.5%)
-4.5A
-4.5
-2.7A
-2.7
CS/WDI
SI
SO
SCK
WP
COMMAND
DECODE &
CONTROL
LOGIC
PROTECT LOGIC
STATUS
REGISTER
EEPROM
ARRAY
8KBITS
2.93V (+/-2.5%)
2.63V (+/-2.5%)
See “Ordering Information” on page 3 for
more details
For Custom Settings, call Intersil.
FN8127 Rev 4.00
November 12, 2015
Page 2 of 21
X5083
Ordering Information
PART NUMBER RESET (ACTIVE LOW)
(Note 1)
PART
MARKING
V
CC
RANGE
(V)
V
TRIP
RANGE
(V)
TEMPERATURE
RANGE (°C)
-40 to 85
4.5-5.5
4.5-4.75
0 to 70
-40 to 85
0 to 70
-40 to 85
4.5-5.5
4.25-4.5
-40 to 85
PACKAGE
(RoHS Compliant)
8 Ld PDIP*
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld TSSOP
PKG.
DWG. #
MDP0031
M8.15E
M8.15E
M8.15E
M8.15E
M8.173
X5083PIZ-4.5A
(No longer available or
X5083P ZAM
supported)
X5083S8Z-4.5A
X5083S8IZ-4.5A (Note 2)
X5083S8Z
X5083S8IZ (Note 2)
X5083V8IZ
(No longer available,
recommended replacement:
X5083S8IZ)
X5083S8Z-2.7A
X5083S8IZ-2.7A*
X5083S8Z-2.7*
X5083S8IZ-2.7*
X5083V8IZ-2.7
(No longer available,
recommended replacement:
X5083S8IZ-2.7)
NOTE:
X5083 ZAL
X5083 ZAM
X5083 Z
X5083 ZI
583 IZ
X5083 ZAN
X5083 ZAP
X5083 ZF
X5083 ZG
583 GZ
2.7-5.5
2.85-3.0
0 to 70
-40 to 85
0 to 70
-40 to 85
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld TSSOP
M8.15E
M8.15E
M8.15E
M8.15E
M8.173
2.7-5.5
2.55-2.7
-40 to 85
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. *Add "-T1" suffix for tape and reel.
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Description
PIN
(SOIC/
PDIP)
1
PIN
TSSOP
3
NAME
FUNCTION
CS/WDI
Chip Select Input.
CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a
nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device,
placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition
on CS is required.
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH
to LOW transition within the watchdog time out period results in RESET going active.
SO
SI
SCK
WP
V
SS
V
CC
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the
serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge
of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in
the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect.
When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the
memory to protect it against inadvertent changes when WP is HIGH, the device operates normally.
Ground
Supply Voltage
2
5
6
3
4
8
7
4
7
8
5
6
2
1
RESET
Reset Output.
RESET is an active LOW, open drain output which goes active whenever V
CC
falls below the
minimum V
CC
sense level. It will remain active until V
CC
rises above the minimum V
CC
sense level for 250ms.
RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable
watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET goes active on power-up at
about 1V and remains active for 250ms after the power supply stabilizes.
FN8127 Rev 4.00
November 12, 2015
Page 3 of 21
X5083
Principles of Operation
Power-on Reset
Application of power to the X5083 activates a power-on reset
circuit. This circuit goes LOW at 1V and pulls the RESET pin
active. This signal prevents the system microprocessor from
starting to operate with insufficient voltage or prior to
stabilization of the oscillator. RESET active also blocks
communication to the device through the SPI interface. When
V
CC
exceeds the device V
TRIP
value for 200ms (nominal) the
circuit releases RESET, allowing the processor to begin
executing code. While V
CC
< V
TRIP
communications to the
device are inhibited.
V
CC
Threshold Reset Procedure
The X5083 is shipped with a standard V
CC
threshold (V
TRIP
)
voltage. This value will not change over normal operating and
storage conditions. However, in applications where the
standard V
TRIP
is not exactly right, or if higher precision is
needed in the V
TRIP
value, the X5083 threshold may be
adjusted. The procedure is described below, and uses the
application of a high voltage control signal.
Setting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a higher voltage
value. For example, if the current V
TRIP
is 4.4V and the new
V
TRIP
is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it is
necessary to reset the trip point before setting the new value.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold voltage to the V
CC
pin and tie the WP pin to the
programming voltage V
P
. Then send a WREN command,
followed by a write of Data 00h to address 01h. CS going HIGH
on the write operation initiates the V
TRIP
programming
sequence. Bring WP LOW to complete the operation.
Note:
This operation also writes 00h to array address 01h.
Low Voltage Monitoring
During operation, the X5083 monitors the V
CC
level and
asserts RESET if supply voltage falls below a preset minimum
V
TRIP
. The RESET signal prevents the microprocessor from
operating in a power fail or brownout condition and terminates
any SPI communication in progress. The RESET signal
remains active until the voltage drops below 1V. It also remains
active until V
CC
returns and exceeds V
TRIP
for 200ms.
When V
CC
falls below V
TRIP
, any communications in progress
are terminated and communications are inhibited until V
CC
exceeds V
TRIP
for t
PURST
.
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native” voltage
level. For example, if the current V
TRIP
is 4.4V and the new
V
TRIP
must be 4.0V, then the V
TRIP
must be reset. When V
TRIP
is reset, the new V
TRIP
is something less than 1.7V. This
procedure must be used to set the voltage to a lower value.
To reset the new V
TRIP
voltage, apply the desired V
TRIP
threshold voltage to the Vcc pin and tie the WP pin to the
programming voltage V
P
. Then send a WREN command,
followed by a write of data 00h to address 03h. CS going HIGH
on the write operation initiates the V
TRIP
programming
sequence. Bring WP LOW to complete the operation.
Note:
This operation also writes 00h to array address 03h.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the WDI input. The microprocessor must toggle the
CS/WDI pin periodically to prevent a RESET signal. The CS/WDI
pin must be toggled from HIGH to LOW prior to the expiration of
the watchdog time out period. The state of two nonvolatile control
bits in the status register determine the watchdog timer period.
The microprocessor can change these watchdog bits with no
action taken by the microprocessor these bits remain
unchanged, even after total power failure.
WP
V
P
= 15-18V
CS
0 1 2 3 4 5 6 7
SCK
16 Bits
SI
06h
WREN
02h
Write
0001h
Address
00h
Data
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23
FIGURE 1. SET V
TRIP
LEVEL SEQUENCE (V
CC
= DESIRED V
TRIP
VALUE)
FN8127 Rev 4.00
November 12, 2015
Page 4 of 21
X5083
WP
V
P
= 15-18V
CS
0 1 2 3 4 5 6 7
SCK
16 Bits
SI
06h
WREN
02h
Write
0003h
Address
00h
Data
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23
FIGURE 2. RESET V
TRIP
LEVEL SEQUENCE (V
CC
> 3V. WP = 15-18V)
V
P
Adjust
V
TRIP
Adj.
1
2
3
4
X5083
8
7
6
5
4.7K
RESET
µC
SCK
SI
SO
CS
Run
FIGURE 3. SAMPLE V
TRIP
RESET CIRCUIT
FN8127 Rev 4.00
November 12, 2015
Page 5 of 21
Microcontroller MCU
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