The second frequency conversion circuit of the satellite receiver

The second frequency conversion circuit of the DBS series satellite receiver is shown in the figure. This circuit has a simpler structure than the above circuit. The first intermediate frequency signal first passes through a 950-1 450 MHz band-pass filter to filter out interference other than the first intermediate frequency. It then goes through two stages of RF amplifiers for wide-band low-noise amplification, and then mixes the frequency with the signal from the second local oscillator. After frequency difference, the second intermediate frequency signal is obtained. The intermediate frequency signal is amplified by AGC to stabilize the signal amplitude, and the buffer and band-remote filter are used to extract the intermediate frequency signal. The frequency of the bandpass filter is 512±13.5 MHZ . It is fixed, so the performance of suppressing adjacent channel interference is not as good as the circuit mentioned above, but because the intermediate frequency it chooses is relatively high (512 MHz) , the ability to suppress image frequency interference is relatively strong. The IF signal is demodulated after multi-stage amplification. This circuit uses a PLL (phase-locked loop) demodulation circuit. The phase-locked loop demodulation circuit is not sensitive to the amplitude changes of the signal, so a special limiting circuit can be omitted. The AFC switch is controlled by a microprocessor (CPU) for easy debugging.