IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS PRESETTABLE
SYNCHRONOUS 4-BIT BINARY
COUNTER WITH SYNCHRONOUS
RESET, 5 VOLT TOLERANT I/O
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in QSOP, SOIC, SSOP, and TSSOP packages
IDT74LVC163A
FEATURES:
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
Outputs (Q
0
to Q
3
) may be preset to a high or low level. A low level at the
parallel enable input (PE) disables the counting action and causes the data
at the data inputs (D
0
to D
3
) to be loaded into the counter on the positive-going
edge of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count enable
inputs (CEP and CET). A low level at the master reset input (MR) sets all
four outputs of the flip-flops (Q
0
to Q
3
) to low level after the next positive-going
transition on the clock (CP) input (provided that the set-up and hold time
requirements for PE are met).
This action occurs regardless of the levels of CP,
PE,
CET, and CEP
inputs. This synchronous reset feature enables the designer to modify the
maximum count with only one external NAND gate.
The look-ahead carry simplifies serial cascading of the counters. Both
count enable inputs (CEP and CET) must be high to count. The CET input
is fed forward to enable the terminal count output (TC). The TC output thus
enabled will produce a high output pulse of a duration approximately equal
to a high level output of Q
0
. This pulse can be used to enable the next
cascaded stage. The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP to CP set-up
time, according to the following formula:
1
tp
(max)
(CP to TC) + t
su
(CEP to CP)
The LVC163A is a synchronous presettable binary counter, which
features an internal look-ahead carry and can be used for high-speed
counting. Synchronous operation is provided by having all the flip-flops
clocked simultaniously on the positive-going edge of the clock (CP).
f
max
=
FUNCTIONAL DIAGRAM
3
4
5
6
STATE DIAGRAM
0
1
2
3
4
D
0
9
D
1
D
2
D
3
PE
PARALLEL LOAD
CIRCUITRY
10
CET
TC
15
15
5
7
CEP
14
2
6
CP
BINARY COUNTER
1
MR
13
Q
0
14
7
Q
1
13
Q
2
12
Q
3
11
12
11
10
9
8
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4949/1
IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
TYPICAL TIMING SEQUENCE
MR
PE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through each
V
CC
or GND
Max
–0.5 to +6.5
–65 to +150
–50 to +50
–50
±100
Unit
V
°C
mA
mA
mA
D0
D1
D2
D3
CP
CEP
CET
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Q0
Q1
Q2
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
C
IN
C
OUT
C
I/O
INHIBIT
Q3
TC
12
RESET PRESET
13
14
15
0
COUNT
1
2
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
Description
Asynchronous Master Reset (Active LOW)
Clock Input (LOW-to-HIGH, Edge-Triggered)
Data Inputs
Count Enable Inputs
Ground (0V)
Parallel Enable Input (Active LOW)
Count Enable Carry Input
Flip-Flop Outputs
Terminal Count Output
Positive Supply Voltage
PIN CONFIGURATION
MR
CP
D
0
D
1
D
2
D
3
CEP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
TC
Q
0
Q
1
Q
2
Q
3
CET
PE
MR
CP
Dx
CEP
GND
PE
CET
Qx
TC
Vcc
SOIC/ SSOP/ TSSOP/ QSOP
TOP VIEW
3
IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE
(1)
OPERATING
MODES
Reset (clear)
Parallel load
Count
Hold
(do nothing)
NOTE:
1. H =
h =
L =
l =
X =
* =
INPUTS
MR
l
h
h
h
h
h
CP
↑
↑
↑
↑
X
X
CEP
X
X
X
h
l
X
CET
X
X
X
h
X
l
PE
X
l
l
h
h
h
Dx
X
l
h
X
X
X
Qx
L
L
H
count
Q
(2)
Q
(2)
OUTPUTS
TC
L
L
*
*
*
L
HIGH Voltage Level
HIGH Voltage level one setup time prior to the LOW-to-HIGH clock transition.
LOW Voltage Level
LOW Voltage level one setup time prior to the LOW-to-HIGH clock transition.
Don’t care
The TC output is HIGH when CET is HIGH and the counter is at Terminal Count (HHHH).
↑
= LOW-to-HIGH clock transition
2. Indicates the state of the referenced output one set up time prior to the LOW-to-HIGH clock transition.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH(2)
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V, V
IN
= GND or V
CC
—
—
—
—
—
–0.7
100
—
±50
–1.2
—
10
µA
V
mV
µA
V
CC
= 3.6V
V
O
= 0 to 5.5V
—
—
±10
µA
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
Test Conditions
Min.
1.7
2
—
—
—
Typ.
(1)
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
µA
V
Unit
V
Quiescent Power Supply Current
Variation
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
—
—
500
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. Clock Pin (CP) requires a minimum V
IH
of 2.5V.
4
IDT74LVC163A
3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, V
CC
= 3.3V ± 0.3V, T
A
= 25°C
Symbol
C
PD
Parameter
Power Dissipation Capacitance
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
—
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.7V
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
W
t
SU
t
SU
t
SU
t
H
t
SK
(o)
Parameter
Propagation Delay
CP to Qx
Propagation Delay
CP to TC
Propagation Delay
CET to TC
Clock Pulse Width, HIGH or LOW
Set-Up Time, Dx to CP
Set-Up Time,
MR, PE
to CP
Set-Up Time, CEP, CET to CP
Hold Time, Dx,
PE,
CEP, CET,
MR
to CP
Output Skew
(2)
Min.
—
—
—
5
3.5
3.5
5.5
0
—
Max.
9
11
8.8
—
—
—
—
—
—
V
CC
= 3.3V ± 0.3V
Min.
—
—
—
4
3
3
5
0
—
Max.
8
9.5
7.8
—
—
—
—
—
500
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
5
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