MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
CMI Coder/Decoder
The MC100SX1230 device consists of a Binary to CMI Coder and CMI
to Binary Decoder with integrated loop back capability. The device is
designed for CMI (Code Mark Inversion) interfaces in transmission
applications supporting either 139.26 Mbit/s E4 or 155.52 Mbit/s STM1
line rates.
MC100SX1230
•
•
•
•
•
•
•
•
•
•
Binary-to-CMI Coder and CMI-to-Binary Decoder
Internal Loop Back Test Capability
Supports SDH or PDH Applications
Low Power
Fully Differential 100K Compatible I/O
VBB Reference Available
75kΩ Input Pulldown Resistors
+5V PECL or –5V ECL Operation
28-Pin Surface Mount PLCC Package
Asynchronous Reset
CMI CODER/DECODER
In normal operation, the coder and decoder operate independently.
Both the coder and decoder operate from a 2X line rate clock. The device
incorporates test circuitry to support loop back bypass so either the coder
input can be routed to the decoder output or the decoder input can be
routed to the coder output. The part is fabricated using Motorola’s proven
MOSAIC III™ advanced bipolar process.
The device provides a VBB output for accepting single-ended inputs.
The VBB pin should only be used as a bias for the MC100SX1230 as its
current sink/source capability is limited. Whenever used, the VBB pin
should be bypassed to ground via a 0.01µF capacitor.
CCLKout CCLKout QCMI QCMI QBIN
25
LCMI
LBIN
VEE
VEE
DCLKin
DCLKin
VBB
26
27
28
1
2
3
4
5
6
7
CMIin
8
BINin
9
10
11
24
23
22
21
QBIN DCLKout
20
19
18
17
16
DCLKout
VCC
VCC
VCCO
VCCO
N/C
N/C
LCMI
RESET CMIin
BINin CCLKin CCLKin
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776-02
PIN NAMES
Pins
CMIin, CMIin
DCLKin, DCLKin
QBIN, QBIN
DCLKout, DCLKout
BINin, BINin
CCLKin, CCLKin
QCMI, QCMI
CCLKout, CCLKout
RESET
LBIN
Function
CMI Input to Decoder
Decoder Clock Input
Binary Output From Decoder
Decoder Clock Output
Binary Input to Coder
Coder Clock Input
CMI Output from Coder
Coder Clock Output
Asynchronous Reset
Control Input for Binary
Loop Back
Control Input for CMI
Loop Back
Pinout: 28-Lead PLCC
(Top View)
15
14
13
12
MOSAIC III is a trademark of Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
4/94
©
Motorola, Inc. 1994
REV 0
MC100SX1230
ABSOLUTE MAXIMUM RATINGS1
Symbol
VEE
VI
IOUT
TA
Power Supply (VCC = 0V)
Input Voltage (VCC = 0V)
Output Current
Operating Temperature Range
Continuous
Surge
Parameter
Value
–8 to 0
0 to –6
50
100
0 to +85
Unit
Vdc
Vdc
mA
°C
VEE
Operating Range
2
–5.7 to 4.2
V
1
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
2
Parametric values specified at: –4.2 to 5.46V
DC CHARACTERISTICS
(VCC = VCCO = GND; VEE = –4.2 to 5.46V)
0°C
Symbol
VOH
VOL
VOHA
VOLA
VIH
VIL
VBB
IIH
IIL
Characteristic
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Reference Voltage
Input HIGH Current
Input LOW Current
0.5
–1165
–1810
–1380
Min
–1025
–1810
–1035
–1610
–880
–1475
–1260
200
0.5
–1165
–1810
–1380
Typ
–955
–1705
Max
–880
–1620
Min
–1025
–1810
–1035
–1610
–880
–1475
–1260
200
0.5
–1165
–1810
–1380
25°C
Typ
–955
–1705
Max
–880
–1620
Min
–1025
–1810
–1035
–1610
–880
–1475
–1260
200
85°C
Typ
–955
–1705
Max
–880
–1620
Unit
mV
mV
mV
mV
mV
mV
V
µA
µA
Condition
Vin = VIH(max) or VIL(min)
Vin = VIH(max) or VIL(min)
Vin = VIH(max) or VIL(min)
Vin = VIH(max) or VIL(min)
IEE
Supply Current
61
122
61
122
70
141
mA
1. 100SX circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is mounted in a test socket
or mounted on a printed circuit board and transverse air greater than 500lfm is maintained.
2. All outputs are loaded with 50Ω to VCC – 2V.
AC CHARACTERISTICS
(VCC = VCCO = GND; VEE = –4.2 to 5.46V)
0 to 85°C
Symbol
Fmax
tpd
Propagation
Delay
CCLKin to CCLKout
CCLKin to QCMI
DCLKin to DCLKout
DCLKin to QBIN
CCLKin to DCLKout
CCLKin to QBIN
DCLKin to QCMI
BINin to CCLKin
CMIin to DCLKin
CCLKin to BINin
DCLKin to CMIin
250
–0.4
150
Note
700
Characteristic
Min
700
650
1000
550
1000
1100
800
–375
140
1000
120
1550
1750
1700
1800
2700
1700
ps
ps
mV
V
ps
20% – 80%
Typ
Max
Unit
MHz
ps
LCMI=LBIN=‘L’
LCMI=LBIN=‘L’
LCMI=LBIN=‘L’
LCMI=‘L’, LBIN=‘H’
LCMI=‘L’, LBIN=‘L’
LCMI=‘H’, LBIN=‘L’
Add 3 CCLKin-Cycles to Delay
Add 4 DCLKin-Cycles to Delay
Add 3 CCLKin-Cycles to Delay
Add 5 DCLKin-Cycles to Delay
Condition
Notes
ts
th
VPP
VCMR
tr, tf
Setup Time
Hold Time
Minimum Input Swing
Common Mode Range
Rise/Fall Times
1. 100SX circuits are designed to meet the AC specifications shown in the table after thermal equilibrium has been established. The circuit is mounted in a test socket
or mounted on a printed circuit board and transverse air greater than 500lfm is maintained.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range
and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range is dependent on VEE and is equal to VEE + 3.0V.
High Performance Frequency
Control Products — BR1334
MOTOROLA
3
MC100SX1230
Applications Information
CMI Code
The CMI code is a 1B2B code. Each information bit is
coded into two transmission bits. A binary 0 is coded to 01,
and a binary 1 is coded alternately to a 00 or a 11, thus there
is at least one transition during every bit period. A typical
data pattern is illustrated in the figure below. Because of the
coding, the data stream is not only DC balanced, but it
contains a rich clock component which aids the clock
recovery process at the receiver. A 2X clock is used by the
MC100SX1230 to ensure that the mid-bit transition of the
data 0 is ideally centered at the CMI encoded output.
0
Binary
0
1
1
0
other end of the cable that ‘real’ data is not being sent. The
device contains a Reset input which should normally be reset
as part of the powering up sequence.
The coder accepts a differential data input (BINin) as well
as a differential clock (CCLKin). The clock signal must be
twice the frequency of the input data signal, i.e. a 155 MBit/s
binary signal requires a 310 MHz clock, for proper operation.
Typical input and output waveforms are shown in Figure 2.
The incoming clock signal is divided by 2 and supplied at the
coder clock output (CLKout). The BINin signal is buffered
before being driven into the input register which clocks in the
binary data. This results in a negative setup time for the
coder. The coded data is output from the coder 3 CCLKin
clock cycles plus normal propagation delay after the binary
data has been supplied.
The decoder accepts a differential data input (CMIin) as
well as a differential clock (DCLK in). The clock signal is
supplied from the external clock extraction circuit and runs at
the coded rate of either 280 MHz or 310 MHz depending on
weather the application is for a PDH system or an SDH
system. The decoder has a latency of 4 clock cycles so the
decoded data is output 4 cycles plus the normal propagation
delay after the input data is captured. Figure 3 illustrates the
decoder operation.
Under certain conditions, the user may require that the
binary data to be coded be routed back to the output of the
decoder to verify proper system operation. This is accom-
plished through the use of the LBIN input control pin. When
this signal is asserted (LBIN = ‘H’), the BINin signal as well
as a divided by 2 version of the CCLKin input is routed to the
QBIN and DCLKout outputs respectively. The BINin to QBIN
output has a latency of 3 CCLK in cycles plus internal
propagation delays. In addition, the AIS signal is generated
and output from the QCMI output. To the receiver the AIS
signal is decoded as a constant logic ‘H’ signal. This
operation is seen in Figure 4.
To complement the binary loop back feature, a CMI loop
back function is also supported. This is accomplished by
asserting the LCMI input control pin (LCMI =‘H’). Under this
condition, the CMI coded input is decoded, then routed
through the coder block to the QCMI output. The CMIin to
QCMI output has a latency of 5 DCLKin cycles plus internal
propagation delays. Figure 5 shows the CMI loop back
operation.
CMI
0
0
1
1
0
Figure 1. CMI Code
Typical Application
In a traditional telecommunications application, the
MC100SX1230 is resident on the line card interface which
contains circuitry to implement the line transmitter and
receiver functions. On the decoder side, a cable equalization
filter followed by a clock recovery/decision circuit are
required to compensate for the cable attenuation and
distortion, extract the 2X clock signal and re-time the CMI
data. On the coder side, a PLL is required to synthesize the
2X coder clock and a conditioning circuit is needed at the
output of the coder to generate the appropriate signal to drive
the cable.
Device Operation
The circuit contains a complete CMI coder and decoder as
well as the support circuitry necessary to perform loop back
of either the Binary input or the CMI input. The operation is
controlled by the LCMI and LBIN inputs. In addition, the
device generates an AIS (Alarm Indication Signal) from the
coder output when the binary loop back state is active
(LBIN=‘H’). The AIS signal indicates to the receiver at the
MOTOROLA
4
High Performance Frequency
Control Products — BR1334
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