CY14B102L-ZSP25XI datasheet, PDF

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CY14B102L-ZSP25XI: DescriptionNon-Volatile SRAM, 256KX8, 25ns, CMOS, PDSO54, ROHS COMPLIANT, TSOP2-54; Categorystorage storage; File Size633KB，21 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CY14B102L-ZSP25XI Overview

Non-Volatile SRAM, 256KX8, 25ns, CMOS, PDSO54, ROHS COMPLIANT, TSOP2-54

CY14B102L-ZSP25XI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	25 ns
JESD-30 code	R-PDSO-G54
JESD-609 code	e3
length	22.41 mm
memory density	2097152 bit
Memory IC Type	NON-VOLATILE SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	54
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3/3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.003 A
Maximum slew rate	0.07 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	10.16 mm
Base Number Matches	1

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ADVANCE

CY14B102L, CY14B102N

2-Mbit (256K x 8/128K x 16) nvSRAM

Features

■

Functional Description

The Cypress CY14B102L/CY14B102N is a fast static RAM, with

a nonvolatile element in each memory cell. The memory is

organized as 256K words of 8 bits each or 128K words of 16 bits

each. The embedded nonvolatile elements incorporate

QuantumTrap technology, producing the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write

cycles, while independent nonvolatile data resides in the highly

reliable QuantumTrap cell. Data transfers from the SRAM to the

nonvolatile elements (the STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM (the RECALL operation) from the nonvolatile memory.

Both STORE and RECALL operations are also available under

software control.

15 ns, 20 ns, 25 ns, and 45 ns access times

Internally organized as 256K x 8 (CY14B102L) or 128K x 16

(CY14B102N)

Hands off automatic STORE on power down with only a small

capacitor

STORE to QuantumTrap

™

nonvolatile elements initiated by

software, device pin, or AutoStore

™

on power down

RECALL to SRAM initiated by software or power up

Infinite read, write, and recall cycles

200,000 STORE cycles to QuantumTrap

20 year data retention

Single 3V +20%, –10% operation

Commercial, Industrial and Automotive temperatures

48-pin FBGA, 44 and 54-pin TSOP II packages

Pb-free and RoHS compliance

Logic Block Diagram

CAP

Address A

- A

[1]

DQ0 - DQ7

CY14B102L

CY14B102N

HSB

BHE

BLE

Note

1. Address A

- A

and Data DQ0 - DQ7 for x8 configuration, Address A

- A

and Data DQ0 - DQ15 for x16 configuration.

Cypress Semiconductor Corporation

Document Number: 001-45754 Rev. *A

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised June 27, 2008

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