Preliminary
EMC326SP16AJ
2Mx16 CellularRAM
Document Title
2Mx16 bit CellularRAM
Revision History
Revision No.
0.0
History
Initial Draft
Draft Date
July 05,2007
Remark
Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
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The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will
answer to your questions about device. If you have any questions, please contact the EMLSI office.
Preliminary
EMC326SP16AJ
2Mx16 CellularRAM
32Mb Async/Page/Burst CellularRAM
FEATURES
- Sigle device supports asynchrous, page and burst operation
- Vcc, VccQ voltages:
1.7V~1.95V VCC
1.7V~1.95V VCCQ
- Random access time: 70ns
- Burst mode READ and WRITE access:
4, 8, 16, or 32 words, or continuous burst
Burst wrap or sequential
Max clock rate: 104 MHz (t
CLK
= 9.62ns) , 133MHz(t
CLK
= 7.5ns)
Burst initial latency: 38.5ns (4 clocks) @ 104 MHz ,
37.5ns(5 clocks) @ 133 MHz
t
ACLK
: 7ns @ 104 MHz , 5.5ns @ 133 MHz
- Page mode READ access:
Sixteen-word page size
Interpage READ access : 70ns
Intrapage READ access : 20ns
- Low power consumption:
Asynchronous READ: <25mA
Intra page READ: <15mA
Initial access, burst READ:
(37.5ns [5 clocks] @ 133 MHz) <40mA
Continuous burst READ: <35mA
Deep power down: < 10uA(max.)
- Low-power features
On-chip temperature compensated self refresh (TCSR)
Partial array refresh (PAR)
Deep Power-down(DPD) mode
OPTIONS
- Configuration: 32Mb (2 megabit x 16)
- Vcc core / VccQ I/O voltage supply: 1.8V
- Timing: 70ns access
- Frequency: 83 MHz, 104 MHz, 133 MHz
- Standby current at 85°C
Low Low Power : 100µA(max)
Low Power
: 120µA(max)
Standard
: 140µA(max)
- Operating temperature range:
Wireless -30°C to +85°C
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Preliminary
EMC326SP16AJ
2Mx16 CellularRAM
Table of Contents
Features .................................................................................................................................................................................
Options ...............................................................................................................................................................................
General Description ................................................................................................................................................................
Functional Description ............................................................................................................................................................
Power-Up Initialization .......................................................................................................................................................
Bus Operating Modes .............................................................................................................................................................
Asynchronous Mode ..........................................................................................................................................................
Page Mode READ Operation ............................................................................................................................................
Burst Mode Operation ........................................................................................................................................................
Mixed-Mode Operation .......................................................................................................................................................
WAIT Operation .................................................................................................................................................................
LB# / UB# Operation...........................................................................................................................................................
Low-Power Operation......... ....................................................................................................................................................
Standby Mode Operation ...................................................................................................................................................
Temperature Compensated Refresh...................................................................................................................................
Partial Array Refresh ..........................................................................................................................................................
Deep Power-Down Operation.............................................................................................................................................
Registers.................................................................................................................................................................................
Access Using CRE .............................................................................................................................................................
Software Access ................................................................................................................................................................
Bus Configuration Register.................................................................................................................................................
Burst Length (BCR[2:0]) Default = Continuous Burst .....................................................................................................
Burst Wrap (BCR[3]) Default = No Wrap ........................................................................................................................
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ...........................................................................
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid / Invalid...................................
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH...................................................................................................
Latency Counter (BCR[13:11]) Default = Three Clock Latency ....................................................................................
Initial Access Latency (BCR[14]) Default = Variable.......................................................................................................
Operating Mode (BCR[15]) Default = Asynchronous Operation.....................................................................................
Refresh Configuration Register...........................................................................................................................................
Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh .....................................................................................
Deep Power-Down (RCR[4]) Default = DPD Disabled ...................................................................................................
Page Mode Operation (RCR[7]) Default = Disabled ......................................................................................................
Device Identification Register..............................................................................................................................................
Electrical Characteristics.........................................................................................................................................................
Timing Requirements..............................................................................................................................................................
Timing Diagrams.....................................................................................................................................................................
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Preliminary
EMC326SP16AJ
2Mx16 CellularRAM
List of Figures
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Functional Block Diagram - 2 meg x 16 ...............................................................................................................
Power-Up Initialization Timing .............................................................................................................................
READ Operation (ADV# LOW) ............................................................................................................................
WRITE Operation (ADV# LOW) ...........................................................................................................................
Page Mode READ Operation (ADV# LOW) .........................................................................................................
Burst Mode READ (4-word burst).........................................................................................................................
Burst Mode WRITE (4-word burst)........................................................................................................................
Refresh Collision During Variable-Latency READ Operation ...............................................................................
Wired or WAIT Configuration .............................................................................................................................
Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation ............................
Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation ..............................
Register READ, Asynchronous Mode, Followed by READ ARRAY Operation ....................................................
Register READ, Synchronous Mode, Followed by READ ARRAY Operation ......................................................
Load Configuration Register ................................................................................................................................
Read Configuration Register ...............................................................................................................................
Bus Configuration Register Definition ..................................................................................................................
WAIT Configuration During Burst Operation ........................................................................................................
Latency Counter (Variable Initial Latency, No Refresh Collision) .........................................................................
Latency Counter (Fixed Latency) ........................................................................................................................
Refresh Configuration Register Mapping .............................................................................................................
AC Input/Output Reference Waveform ................................................................................................................
AC Output Load Circuit ........................................................................................................................................
Initialization Period ..............................................................................................................................................
DPD Entry and Exit Timing Parameters ...............................................................................................................
Asynchronous READ ...........................................................................................................................................
Asynchronous READ Using ADV# .......................................................................................................................
PAGE MODE READ ...........................................................................................................................................
Single-Access Burst READ Operation - Variable Latency ....................................................................................
4-Word Burst READ Operation - Variable Latency ...............................................................................................
Single-Access Burst READ Operation - Fixed Latency ........................................................................................
4-Word Burst READ Operation - Fixed Latency ...................................................................................................
READ Burst Suspend ..........................................................................................................................................
Burst READ at End-of-Row (Wrap off) ................................................................................................
Burst READ Row Boundary Crossing ..................................................................................................................
CE# - Controlled Asychronous WRITE ................................................................................................................
LB#/UB# - Controlled Asychronous WRITE .........................................................................................................
WE# - Controlled Asychronous WRITE ...............................................................................................................
Asynchronous WRITE Using ADV# .....................................................................................................................
Burst WRITE Operation - Variable Latency Mode ................................................................................................
Burst WRITE Operation - Fixed Latency Mode ....................................................................................................
Burst WRITE at End-of-Row (Wrap off) ...............................................................................................................
Burst WRITE Row Boundary Crossing ................................................................................................................
Burst WRITE Followed by Burst READ ................................................................................................................
Burst READ Interrupted by Burst READ or WRITE ..............................................................................................
Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode .....................................................
Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode .........................................................
Asynchronous WRITE Followed by Burst READ .................................................................................................
Asynchronous WRITE (ADV# LOW) Followed by Burst READ ...........................................................................
Burst READ Followed by Asynchronous WRITE (WE# - Controlled) ...................................................................
Burst READ Followed by Asynchronous WRITE Using ADV# .............................................................................
Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW .............................................................
Asynchronous WRITE Followed by Asynchronous READ ...................................................................................
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Preliminary
EMC326SP16AJ
2Mx16 CellularRAM
List of Tables
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PIN Descriptions ......................................................................................................................................................
Bus Operations .........................................................................................................................................................
Sequence and Burst Length .....................................................................................................................................
Drive Strength ..........................................................................................................................................................
Variable Latency Configuration Codes......................................................................................................................
Fixed Latency Configuration Codes..........................................................................................................................
Address Patterns for PAR(RCR[4] =1)......................................................................................................................
Device Identification Register Mapping ....................................................................................................................
Absolute Maximum Ratings .....................................................................................................................................
Electrical Characteristics and Operating Conditions .................................................................................................
Deep Power-Down Specifications ............................................................................................................................
Capacitance .............................................................................................................................................................
Asynchronous READ Cycle Timing Requirements ...................................................................................................
Burst READ Cycle Timing Requirements .................................................................................................................
Asynchronous WRITE Cycle Timing Requirements .................................................................................................
Burst WRITE Cycle Timing Requirements ...............................................................................................................
Initialization and DPD Timing Parameters ................................................................................................................
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