EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
Document Title
512K x 32 x 4Banks Low Power SDRAM Specificaton
Revision History
Revision No.
0.0
0.1
Initial Draft
DC parameter values are changed
DC parameter values are changed.
Wafer spec & PAD allocation are attached.
PAD coordinates are not fixed (TBD).
Special MRS mode (Wrap off) supported.
Pad allocation changed.
(NC Pad added to right bottom)
Pad coordinates are updated.
Pad allocation changed. (BA0,BA1)
DC parameter values are revised.
History
Draft Date
Apr 7 , 2006
Jul 21 , 2006
Remark
Draft
Advanced
0.2
Sep 2 , 2006
Advanced
0.3
0.4
0.5
0.6
Sep 21 , 2006
Dec 6 , 2006
Dec 19 , 2006
Sep 10 , 2007
Advanced
Advanced
Advanced
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Emerging Memory & Logic Solutions Inc.
Zip Code : 690-717
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
512K x 32Bit x 4 Banks Low Power SDRAM
FEATURES
1.8V power supply.
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length(1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation.
Special Function Support.
. PASR(Partial Array Self Refresh).
. Internal auto TCSR
(Temperature Compensated Self Refresh)
. DS (Driver Strength)
. Deep power down
DQM for masking.
Auto refresh.
64 refresh period (4K cycle).
Commercial Temperature Operation (-0 ~ 70 )
Extended Temperature Operation (-25 ~ 85 )
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GENERAL DESCRIPTION
The EMLS232UA series is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 534,288 words by 32 bits,
fabricated with Ramsway’s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock and I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
lengths and programmable latencies allow the same device to be
useful for a variety of high bandwidth and high performance mem-
ory system applications.
ORDERING INFORMATION
Part No.
EMLS232UAW-6(E)
NOTE
:
1. In case of 40 Frequency, CL1 can be supported.
2. Ramsway are not designed or manufactured for use in a device or system that is used under circumstance in which human life is
potentially at stake. Please contact to the memory marketing team in ramsway when considering the use of a product
contained herein for any specific purpose, such as medical,aerospace, nuclear, military, vehicular or undersea repeater use.
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Max Freq.
133
(CL3), 100
(CL2)
Interface
LVCMOS
Package
Wafer Biz.
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
General Wafer Specifications
Process Technology : 0.125um Trench DRAM Process
Wafer thickness : 725 +/- 25um
Typical Pad Open Size : 70.2um x 70.2um
Minimum Pad Pitch : 93.6um
Wafer Diameter : 8-inch
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Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
PAD FUNCTION DESCRIPTION
Pad
CLK
CS
CKE
Name
System clock
Chip select
Clock enable
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
10
,
Column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.: DQ
0 ~ 31
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity
This pin is recommended to be left No Connection on the device.
A
0
~ A
10
Address
BA
0
~ BA
1
RAS
CAS
WE
DQM0~DQM3
DQ
0 ~ n
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C/RFU
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
Rev 0.6
EMLS232UA Series
512K x 32 x 4Banks Low Power SDRAM
FUNCTIONAL BLOCK DIAGRAM
LWE
LDQM
I/O Control
Data Input Register
Bank Select
512K x 32
Sense AMP
Row Decoder
Row Buffer
512K x 32
512K x 32
512K x 32
Refresh Counter
Output Buffer
DQi
Address Register
CLK
ADD
LCBR
Column Decoder
Col. Buffer
Latency & Burst Length
Programming Register
LRAS
LCKE
LRAS
LCBR
LWE
LCAS
Timing Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM0~DQM3
Rev 0.6
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