Product Specification
PE4246
Product Description
The PE4246 RF Switch is designed to cover a broad range of
applications from 1 to 5000 MHz. It is non-reflective at both
RF1 and RF2 ports. This SPST switch integrates a single-pin
CMOS control interface, and provides low insertion loss while
operating with extremely low bias from a single +3-volt supply.
In a typical application, the high isolation PE4246 can replace
multiple RF switches of lesser isolation performance. It is
offered in a small 3x3 mm DFN package.
The PE4246 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Diagram
Peregrine Specification
71/0008
RF1
ESD
ESD
Absorptive SPST UltraCMOS™
RF Switch: 1 - 5000 MHz
Features
Non-reflective 50-ohm RF switch
50-ohm (0.25 watt) terminations
High isolation: 55 dB at 1000 MHz,
48 dB at 3000 MHz
Low insertion loss: 0.8 dB at 1000 MHz,
0.9 dB at 3000 MHz
High linearity: +33 dBm input 1dB
compression point
CMOS/TTL single-pin control
Single +3-volt supply operation
Extremely low bias: 33
μA
@ 3 V
Available in a 6-lead DFN package
CMOS
Control
Driver
CTRL
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3 V
(ZS = ZL = 50
Ω)
EN
D
Parameter
Condition
O
Minimum
1
50
50
F
Typical
Maximum
5000
30/24
0.8
0.9
1.0
1.3
49
45
43
40
11
30
50
15
2
55
48
46
44
20
33
1.0
1.1
1.3
1.8
RF2
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Figure 2. Package Type
6-lead DFN
Units
MHz
dBm
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
mV
pp
μs
Operation Frequency
1
Operating Power
CTRL=1/CTRL=0
1-2000 MHz
2000-3000 MHz
3000-4000 MHz
4000-5000 MHz
1-2000 MHz
2000-3000 MHz
3000-4000 MHz
4000-5000 MHz
1-5000 MHz
Insertion Loss
Isolation
Return Loss
Input 1 dB Compression
Input IP3
Video Feedthrough
2
Switching Time
3
1-5000 MHz
1-5000 MHz
Notes: 1. Device linearity will begin to degrade below 1 MHz.
2. The DC transient at the output of the switch when the control voltage is switched from Low to High or High to Low in a 50
Ω
test set-up,
measured with 1ns risetime pulses and 500 MHz bandwidth.
3. Note Absolute Maximum ratings in Table 3.
Document No. 70-0090-09
│
www.psemi.com
©2003-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 8
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. patents: http://patents.psemi.com
PE4246
Product Specification
Figure 3. Pin Configuration
V
DD
GND
1
Exposed
Solder Pad
(bottom side)
Device Description
The
PE4246 high-isolation SPST RF Switch is
6
RF2
2
5
GND
RF1
3
4
CTRL
designed to support a variety of applications
where high isolation performance is demanded
and a non-reflective input and output is desired.
This switch is able to replace multiple lesser
performing switches in a very small 3x3 mm DFN
footprint.
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Table 4. Operating Ranges
Parameter
Min
2.7
V
DD
Power Supply
Typ
3.0
33
Max
3.3
40
85
5
Unit
V
μA
°C
V
V
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
Pin
Name
V
DD
GND
RF1
CTRL
GND
RF2
Description
Nominal 3 V supply connection.
1
Ground connection.
3
RF port.
2
CMOS or TTL logic level:
High = RF1 to RF2 signal path
Low = RF1 isolated from RF2
Ground connection.
3
RF port.
2
I
DD
Power Supply Current
(V
DD
= 3 V, V
CNTL
= 3 V)
T
OP
Operating temperature
Control Voltage High
Control Voltage Low
-40
0.7xV
DD
0
0.3xV
DD
F
Unit
V
V
°C
dBm
V
Table 5. Control Logic Truth Table
Control Voltage
Signal Path
RF1 to RF2
RF1 isolated from RF2
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Notes: 1. A bypass capacitor should be placed as close as possible
to the pin.
2. Both RF pins must be DC blocked by an external capacitor
or held at 0 V
DC
.
3. The exposed pad must be soldered to the ground plane for
proper switch performance.
O
Min
-0.3
-0.3
-65
Control Logic
The control logic input pin (CTRL) is typically driven by
a 3-volt CMOS logic level signal, and has a threshold of
50% of V
DD
. For flexibility to support systems that have
5-volt control logic drivers, the control logic input has
been designed to handle a 5-volt logic HIGH signal. (A
minimal current will be sourced out of the V
DD
pin when
the control logic input voltage level exceeds V
DD
.)
EN
D
Symbol
V
DD
V
I
Table 3. Absolute Maximum Ratings
Parameter/Condition
Power supply voltage
Max
4.0
5.5
Voltage on CTRL input
Storage temperature
Input power (50
Ω),
CTRL=1/CTRL=0
T
ST
P
IN
150
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 3.
33/24
200
V
ESD
ESD voltage
(Human Body Model)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™ de-
vices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE4246 in
the 6-lead 3x3 DFN package is MSL1.
©2003-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
Document No. 70-0090-09
│
UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. patents: http://patents.psemi.com
PE4246
Product Specification
Typical Performance Data @ 25 °C (Unless Otherwise Noted)
Figure 4. Insertion Loss
T = -40 °C to 85 °C
Figure 5. Input 1dB Compression Point and IIP3
-40 C
-0.5
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50
IIP3
IIP3 (dBm)
40
30
Input 1dB Compression
0
60
60
50
1dB Compression Point (dBm)
Insertion Loss (dB)
-1
85 C
-1.5
25 C
40
-2
30
-2.5
F
20
5000
-3
0
1000
2000
3000
4000
0
1000
2000
3000
4000
20
5000
Frequency (MHz)
Frequency (MHz)
Figure 6. Isolation
EN
D
0
-20
Isolation (dB)
-40
-60
-80
-100
0
1000
2000
3000
4000
5000
Frequency (MHz)
Document No. 70-0090-09
│
www.psemi.com
O
©2003-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 8
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. patents: http://patents.psemi.com
PE4246
Product Specification
Typical Performance Data @ +25 °C
Figure 7. RF1 Return Loss (CTRL = High)
Figure 8. RF2 Return Loss (CTRL = High)
-5
-10
Return Loss (dB)
-15
-20
-25
F
5000
0
0
-5
-10
Return Loss (dB)
-15
-20
-25
-30
-35
5000
0
-30
0
1000
2000
3000
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-5
-10
Return Loss (dB)
-15
-20
-25
-30
4000
1000
2000
3000
4000
5000
Frequency (MHz)
Frequency (MHz)
0
0
Figure 9. RF1 Return Loss (CTRL = Low)
O
3000
4000
Figure 10. RF2 Return Loss (CTRL = Low)
EN
D
0
-5
-10
Return Loss (dB)
-15
-20
-25
-30
-35
0
1000
2000
1000
2000
3000
4000
5000
Frequency (MHz)
Frequency (MHz)
©2003-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 8
Document No. 70-0090-09
│
UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. patents: http://patents.psemi.com
PE4246
Product Specification
Evaluation Kit
The SPST Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4246 SPST switch. The RF1 port is connected
through a 50
Ω
transmission line to the top left
SMA connector, J1. The RF2 port is connected
through a 50
Ω
transmission line to the top right
SMA connector, J2. A through transmission line
connects SMA connectors J3 and J4. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide model with
trace width of 0.0476”, trace gaps of 0.030”,
dielectric thickness of 0.028”, metal thickness of
0.0021” and
εR
of 4.3. Note that the predominate
mode for these transmission lines is coplanar
waveguide with a ground plane.
J5 and J6 provide a means for controlling DC and
digital inputs to the device. J6-1 is connected to
the device V
DD
input. J5-1 is connected to the
device CTRL input. J5-2 and J6-2 are GND
connections. A decoupling capacitor (100 pF) is
provided on both CTRL and V
DD
traces. It is the
responsibility of the customer to determine proper
supply decoupling for their design application.
Removing these components from the evaluation
board has not been shown to degrade RF
performance.
Figure 11. Evaluation Board Layouts
Peregrine Specification 101/0102
O
EN
D
Document No. 70-0090-09
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F
Figure 12. Evaluation Board Schematic
Peregrine Specification 102/0134
©2003-2010 Peregrine Semiconductor Corp. All rights reserved.
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