DRAM MODULE
KMM332F203CS-L
KMM332F213CS-L
KMM332F203CS-L & KMM332F213CS-L Fast Page with EDO Mode
2M x 32 DRAM SODIMM using 2MX8, 4K & 2K Ref., 3.3V, Low power/Self-Refresh
GENERAL DESCRIPTION
The Samsung KMM332F20(1)3CS is a 2Mx32bits Dynamic
RAM high density memory module. The Samsung
KMM332F20(1)3CS consists of four CMOS 2Mx8bits DRAMs
in 28-pinTSOPII packages mounted on a 72-pin four layer zig-
zag glass-epoxy substrate. A 0.1 or 0.22uF decoupling capac-
itor is mounted on the printed circuit board for each DRAM.
The KMM332F20(1)3CS is a Small Out-line Dual In-line Mem-
ory Module with edge connections and is intended for mount-
ing into 72-pin dual readout zigzag edge connector sockets.
FEATURES
• Part Identification
- KMM332F203CS-L5/L6
(4096 cycles/128ms Ref, TSOP, Low Power, 50/60ns)
- KMM332F213CS-L5/L6
(2048 cycles/128ms Ref, TSOP, Low Power, 50/60ns)
• Fast Page with EDO Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• Self refresh capability
• LVTTL compatible inputs and outputs
• Single +3.3V±0.3V power supply
• JEDEC standard PDPin & pinout (72pin)
• PCB : Height(1000mil), single sided component
PERFORMANCE RANGE
Speed
-L5
-L6
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
t
HPC
25ns
30ns
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
CC
PD1
A0
A1
A2
A3
A4
A5
A6
A10
NC
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A7
A11
V
CC
A8
A9
NC
RAS2
DQ16
NC
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
DQ18
DQ19
V
SS
CAS0
CAS2
CAS3
CAS1
RAS0
NC
NC
W
NC
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
NC
DQ27
DQ28
DQ29
DQ31
DQ30
V
CC
DQ32
DQ33
DQ34
NC
PD2
PD3
PD4
PD5
PD6
PD7
V
SS
PIN NAMES
Pin Name
A0 - 11
A0 - 10
DQ(0 -7,9-16,
18-25,27-34)
W
RAS0, RAS2
CAS0 - CAS3
PD1 -PD7
V
CC
V
SS
NC
Function
Address Inputs (4K ref)
Address Inputs (2K ref)
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+3.3V)
Ground
No Connection
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
PD5
PD6
PD7
50NS
V
SS
NC
V
SS
NC
V
SS
V
SS
NC
60NS
V
SS
NC
V
SS
NC
NC
NC
NC
* Pin Connection Charging Available
NOTE : A11 is used for only KMM332F203CS (4K ref.)
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
U0
DQ4
DQ5
DQ6
A0-
w A11(A10) DQ7
KMM332F203CS-L
KMM332F213CS-L
CAS0
RAS0
CAS
RAS
OE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CAS1
CAS
RAS
OE
DQ0
DQ1
DQ2
DQ3
U1
DQ4
DQ5
DQ6
A0-
w A11(A10) DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
CAS2
RAS2
CAS
RAS
OE
DQ0
DQ1
DQ2
DQ3
U2
DQ4
DQ5
DQ6
A0-
w A11(A10) DQ7
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
CAS3
CAS
RAS
OE
DQ0
DQ1
DQ2
DQ3
U3
DQ4
DQ5
DQ6
A0-
w A11(A10) DQ7
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
W
A0-A11(A10)
V
CC
.1uF or .22uF Capacitor
for each DRAM
V
SS
To all DRAMs
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
KMM332F203CS-L
KMM332F213CS-L
Rating
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
4
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to
V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*1 : V
CC
+1.3V/15ns, Pulse width is measured at V
CC
.
*2 : -1.3V/15ns, Pulse width is measured at V
SS
.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3
*2
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3
*1
0.8
Unit
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
KMM332F203CS
KMM332F213CS
Min
Max
Min
Max
I
CC1
-L5
-
360
-
440
-
-
-L6
320
400
I
CC2
Don′t care
-
4
-
4
I
CC3
-L5
-
360
-
440
-
-L6
-
320
400
-
I
CC4
-L5
-
320
360
-
-L6
-
280
320
I
CC5
Don′t care
-
0.8
-
0.8
I
CC6
-L5
-
360
-
440
-
-L6
-
320
400
I
CC7
Don′t care
-
1000
-
1000
I
CCS
Don′t care
-
800
-
800
I
I(L)
-20
20
-20
20
Don′t care
I
O(L)
-5
5
-5
5
V
OH
2.4
-
2.4
-
Don′t care
V
OL
-
0.4
-
0.4
I
CC1
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
I
CC4
: EDO Mode Current * (RAS=V
IL
, CAS cycling :
t
HPC
=min)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=0.2V)
DQ0-31=Don′t care,
t
RC
=31.25us (4K Ref.),62.5us (2K Ref.) ,
t
RAS
=
t
RAS
min~300ns
Iccs : Self Refresh Current (RAS=CAS-V
IL
, W=OE=A0-A11=V
CC
-0.2V or 0.2V, DQ0-DQ31=V
CC
-0.2V,0.2V or OPEN)
I
I(L)
: Input Leakage Current (Any input 0≤V
IN
≤V
CC
+0.5V, all other pins not under test=0 V)
I
O(L)
: Output Leakage Current(Data Out is disabled, 0V≤V
OUT
≤V
CC
)
V
OH
: Output High Voltage Level (I
OH
= -2mA)
V
OL
: Output Low Voltage Level (I
OL
= 2mA)
Symbol
Speed
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
uA
uA
V
V
* NOTE : I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle,
t
HPC
.
DRAM MODULE
CAPACITANCE
(T
A
= 25°C, Vcc=3.3V, f = 1MHz)
Item
Input capacitance[A0-A11(A10)]
Input capacitance[W]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-7,9-16,18-25,27-34]
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ
Min
-
-
-
-
-
KMM332F203CS-L
KMM332F213CS-L
Max
40
45
30
20
20
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=3.3V±0.3V. See notes 1,2.)
Test condition : V
ih
/V
il
=2.0/0.8V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
Random read or write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Data hold time
Refresh period
Write command set-up time
CAS setup time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS to CAS precharge time
Symbol
Min
-5
Max
50
13
25
3
3
2
30
50
13
43
8
20
15
5
0
10
0
8
25
0
0
0
10
10
13
8
0
8
128
0
5
10
5
0
5
10
5
10K
37
25
10K
13
50
3
3
2
40
60
15
50
10
20
15
5
0
10
0
10
30
0
0
0
10
10
15
10
0
10
128
10K
45
30
10K
15
50
Min
110
60
15
30
90
-6
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
7
8
8
8
8
13
4
10
3,4,10
3,4,5
3,10
3
6,11,12
2
Unit
Note
t
RC
t
RAC
t
CAC
t
AA
t
CLZ
t
CEZ
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
DRAM MODULE
AC CHARACTERISTICS
(Countinued)
Test condition : V
ih
/V
il
=2.0/0.8V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
CAS precharge time (CBR counter test cycle)
Access time from CAS precharge
Hyper page mode cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
W pulse width
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
Symbol
Min
-5
Max
28
25
8
50
30
10
10
5
3
3
15
5
100
90
-50
13
13
200K
30
10
60
35
10
10
5
3
3
15
5
100
110
-50
Min
20
20
KMM332F203CS-L
KMM332F213CS-L
-6
Max
Unit
ns
35
ns
ns
ns
200K
ns
ns
ns
ns
ns
15
15
ns
ns
ns
ns
us
ns
ns
Note
t
CPT
t
CPA
t
HPC
t
CP
t
RASP
t
RHCP
t
WRP
t
WRH
t
DOH
t
REZ
t
WEZ
t
WED
t
WPE
t
RASS
t
RPS
t
CHS
3
13
6,11,12
6,11
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. V
IH
(min) and V
IL
(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V
IH
(min) and V
IL
(max) and are assumed to be 5ns
for all inputs.
3. Measured with a load equivalent to 1 TTL loads and 100pF.
4. Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
5. Assumes that
t
RCD
≥
t
RCD
(max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
7.
t
WCS
is non restrictive operating parameter.
It is included in the data sheet as electrical characteristics only.
If
t
WCS
≥
t
WCS
(min) the cycle is an early write cycle and the data
out pin will remain high impedance for the duration of the cycle.
8. Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9. These parameters are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
10. Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can
be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit access time is con-
trolled by
t
AA
.
11.
t
CEZ
(max),
t
REZ
(max),
t
WEZ
(max) and
t
OEZ
(max) define the
timeat which the output achieves the open circuit condition and
are not referenced to output voltage level.
12. If RAS goes to high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes to high before RAS high going , the open circuit condition
of the output is achieved by RAS going.
13.
t
ASC
≥
t
CP
min
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