C161RI
16-Bit CMOS Single-Chip Microcontroller
User’s Manual Version 1.0 05.98
ht
tp
://
se ww
m w
ic .s
on ie
du me
ct ns
or .d
/ e
/
05.98
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
©
Siemens AG 1998.
All Rights Reserved.
Attention please!
As far as patents or other rights of third par-
ties are concerned, liability is only assumed
for components, not for applications, pro-
cesses and circuits implemented within com-
ponents or assemblies.
The information describes the type of compo-
nent and shall not be considered as assured
characteristics.
Terms of delivery and rights to change design
reserved.
For questions on technology, delivery and
prices please contact the Semiconductor
Group Offices in Germany or the Siemens
Companies and Representatives worldwide
(see address list).
Due to technical requirements components
may contain dangerous substances. For in-
formation on the types in question please
contact your nearest Siemens Office, Semi-
conductor Group.
Siemens AG is an approved CECC manufac-
turer.
Packing
Please use the recycling operators known to
you. We can also help you – get in touch with
your nearest sales office. By agreement we
will take packing material back, if it is sorted.
You must bear the costs of transport.
For packing material that is returned to us un-
sorted or which we are not obliged to accept,
we shall have to invoice you for any costs in-
curred.
Components used in life-support devices
or systems must be expressly authorized
for such purpose!
Critical components
1
of the Semiconductor
Group of Siemens AG, may only be used in
life-support devices or systems
2
with the ex-
press written approval of the Semiconductor
Group of Siemens AG.
1 A critical component is a component used
in a life-support device or system whose
failure can reasonably be expected to
cause the failure of that life-support de-
vice or system, or to affect its safety or ef-
fectiveness of that device or system.
2 Life support devices or systems are in-
tended (a) to be implanted in the human
body, or (b) to support and/or maintain
and sustain human life. If they fail, it is
reasonable to assume that the health of
the user may be endangered.
C161RI
Revision History:
Previous Releases:
Page
Subjects
Version 1.0 05.98
-
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@siemens-scg.com
C161RI
General Information
Table of Contents
1
1.1
1.2
1.3
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3
3.1
3.2
3.3
3.4
3.5
4
4.1
4.2
4.3
4.4
4.5
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
6
6.1
6.2
6.3
7
7.1
7.2
7.3
Page
1-1
1-2
1-4
1-7
Introduction.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . . . . . . .
Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architectural Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
High Instruction Bandwidth / Fast Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
The On-chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
The On-chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Memory Organization.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Internal ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Internal RAM and SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
The On-Chip XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
The Central Processing Unit (CPU)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Particular Pipeline Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Interrupt and Trap Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . . . . . . . . 5-13
Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Clock Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Ports.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Functions of PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-2
6-3
6-6
7-1
7-6
7-7
7-9
Semiconductor Group
I-1
1998-05-01
C161RI
General Information
Table of Contents
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
8
9
9.1
9.2
9.3
9.4
9.5
9.6
10
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
11
11.1
11.2
11.3
11.4
11.5
12
12.1
12.2
12.3
12.4
12.5
13
13.1
13.2
Alternate Functions of PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Functions of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Functions of Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Functions of Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Functions of Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Functions of Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
7-10
7-12
7-13
7-15
7-16
7-20
7-20
7-23
7-23
7-26
7-27
Dedicated Pins
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
The External Bus Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
External Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Programmable Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
READY Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
Controlling the External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
EBC Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
The XBUS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
The General Purpose Timer Units.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Timer Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
GPT1 Core Timer T3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
GPT1 Auxiliary Timers T2 and T4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Interrupt Control for GPT1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
Timer Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
GPT2 Core Timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
GPT2 Auxiliary Timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
Interrupt Control for GPT2 Timers and CAPREL . . . . . . . . . . . . . . . . . . . . . . . . 10-30
The Asynchronous/Synchronous Serial Interface
. . . . . . . . . . . . . . . . . . . . . 11-1
Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
ASC0 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
ASC0 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
The High-Speed Synchronous Serial Interface
. . . . . . . . . . . . . . . . . . . . . . . . 12-1
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
SSC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
The Watchdog Timer (WDT)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Operation of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Reset Source Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Semiconductor Group
I-2
1998-05-01
京公网安备 11010802033920号
EEWORLD
