HIGH-PERFORMANCE
RF MODULE
RXM-900-HP3-xxx
WIRELESS MADE SIMPLE
®
HP3 SERIES RECEIVER MODULE DATA GUIDE
DESCRIPTION
The HP3 RF receiver module offers complete
HP SERIES RF RECEIVER
compatibility and numerous enhancements
0.780"
RXM-900-HP3-SP*
over previous generations. The HP3 is
designed for the cost-effective, high-
performance wireless transfer of analog or
0.236"
digital information in the popular 902-928MHz
SIP Style
band. All HP3 Series modules feature eight
1.950"
parallel selectable channels, but versions are
HP SERIES RF RECEIVER
also available which add serial selection of 100
0.750"
RXM-900-HP3-SP*
channels. To ensure reliable performance, the
receiver employs FM / FSK demodulation and
0.190"
an advanced dual-conversion microprocessor-
SMD Style
controlled synthesized architecture. The
Figure 1: Package Dimensions
receiver is pin- and footprint-compatible with all
previous generations, but its overall physical size has been reduced. Both SMD and
pinned packages are available. When paired with an HP3 transmitter, a reliable link
is created for transferring analog and digital information up to 1,000 feet. (under
optimal conditions). As with all Linx modules, the HP3 requires no tuning or additional
RF components (except an antenna), making integration straightforward even for
engineers without prior RF experience.
LOT 10000
Pin Spacing: 0.1"
LOT 10000
1.940"
FEATURES
APPLICATIONS INCLUDE
Wireless Networks / Data Transfer
8 parallel / 100 serial (PS Versions)
Wireless Analog / Audio
user-selectable channels
Home / Industrial Automation
FM / FSK demodulation for outstanding
Remote Access / Control
performance and noise immunity
Remote Monitoring / Telemetry
Exceptional sensitivity (-100dBm typical)
Long-Range RFID
Wide-range analog capability including
MIDI Links
audio (50Hz to 28kHz)
Voice / Music / Intercom Links
RSSI and Power-down lines
Precision frequency
ORDERING INFORMATION
synthesized architecture
PART #
DESCRIPTION
No external RF
components required
RXM-900-HP3-PPO
HP3 Receiver (SIP 8 CH only)
Compatible with previous
RXM-900-HP3-PPS
HP3 Receiver (SIP 8p / 100s CH)
HP Series modules
RXM-900-HP3-SPO
HP3 Receiver (SMD 8 CH only)
High data rate
RXM-900-HP3-SPS
HP3 Receiver (SMD 8p / 100s CH)
(up to 56kbps)
MDEV-900-HP3-PPS-USB
HP3 Development Kit (Pinned Pkg.)
Wide supply range
(2.8 to 13.0VDC)
MDEV-900-HP3-PPS-RS232
HP3 Development Kit (Pinned Pkg.)
Direct serial interface
MDEV-900-HP3-SPS-USB
HP3 Development Kit (SMD Pkg.)
Pinned and SMD packages
MDEV-900-HP3-SPS-RS232 HP3 Development Kit (SMD Pkg.)
Wide temperature range
Receivers are supplied in tubes of 10 pcs.
(-30°C to +85°C)
Revised 1/28/08
ELECTRICAL SPECIFICATIONS
Parameter
POWER SUPPLY
Operating Voltage
Supply Current
Power-Down Current
RECEIVE SECTION
Receive Frequency Range
Center Frequency Accuracy
Channel Spacing
First IF Frequency
Second IF Frequency
Noise Bandwidth
–
100
50
0.8
–
–
–
–
-94
60
–
–
–
–
–
R
OUT
–
–
-57
54
57
50
24
70
80
–
1.6
–
–
–
–
-100
-107
230
–
17
–
µA
dBm
dB
mV/dB
V
dBm
dB
dB
Ω
V
CC
-0.3
–
V
CC
VDC
kohms
0.0
–
0.5
VDC
6
6
–
7
8,9
4
4
4
4
4
4
4
1
ABSOLUTE MAXIMUM RATINGS
Typical
3.0
19.0
5.6
–
+50
250
34.7
10.7
280
–
–
1.1
2.0
VAC
5
28,000
Hz
4
56,000
bps
–
–
kHz
–
–
MHz
4
–
MHz
4
–
kHz
3
kHz
927.62
MHz
3
10.0
µA
2
21.0
mA
1
13.0
VDC
–
Max.
Units
Notes
Designation
V
CC
I
CC
I
PDN
F
C
-50
–
–
–
N
3DB
–
–
–
902.62
–
16.0
2.8
Min.
Supply Voltage V
CC
Any Input or Output Pin
Operating Temperature
Storage Temperature
Soldering Temperature
-0.3
-0.3
-30
-45
+260°C
to
+18.0
to
V
CC
to
+85
to
+85
for 10 seconds
VDC
VDC
°C
°C
*NOTE*
Exceeding any of the limits of this section may lead to permanent
damage to the device. Furthermore, extended operation at these maximum
ratings may reduce the life of this device.
PERFORMANCE DATA
Data Rate
Analog / Audio Bandwidth
Analog / Audio Output Level
Data Output:
Logic Low
Logic High
Output Impedance
Data Output Source Current
Receiver Sensitivity
RSSI:
Dynamic Range
Gain
Voltage With No Carrier
Spurious Emissions
Interference Rejection:
FC±1MHz
FC±5MHz
ANTENNA PORT
RF Input Impedance
TIMING
Receiver Turn-On Time:
via V
CC
via PDN
Channel Change Time
Max time between transitions
ENVIRONMENTAL
Operating Temperature Range
–
-30
–
+85
T4
T3
T2
T1
–
–
–
–
–
–
–
–
7.0
3.0
1.5
20
mSec
mSec
mSec
mSec
4
4
4
4
These performance parameters
are based on module operation at
25°C from a 3.0VDC supply unless
otherwise
noted.
Figure
2
illustrates
the
connections
necessary
for
testing
and
operation. It is recommended all
ground pins be connected to the
ground plane. The pins marked NC
have no electrical connection.
PC
PC
PC
5VDC
PC
ANT
GND
GND
GND
GND
GND
GND
GND
NC
CS0
CS1 / SS CLOCK
CS2 / SS DATA
PDN
RSSI
MODE
VCC
AUDIO
DATA
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 2: Test / Basic Application Circuit
TYPICAL PERFORMANCE GRAPHS
PDN
3.0
RSSI VOLTAGE (V)
RX DATA
2
2.5
2.0
1.5
1.0
-110
CH1 1.00V
CH2 2.00V
500uS
-100
-90
-80
-70
-60
-50
-40
Delta 1.920mS
RF INPUT (dBm)
Figure 3: RX Enabled to Valid Data
°
C
4
Figure 4: Receiver RSSI
10
-6
Table 1: HP3 Series Receiver Specifications
RX OFF
Notes
1. Over the entire operating voltage range.
2. With the PDN pin low.
3. Serial mode.
4. Characterized, but not tested.
5. With 1kHz sine wave @ 115kHz transmitter deviation
6. No load.
7. With 1V output drop.
8. For 10
-5
@ 9,600bps.
9. At specified center frequency.
Page 2
10
-5
RX ON >-35dBm
BER
10
-4
10
-3
1
CH1 500mV
1mS
-92 -93 -94
-95
Delta 4.080mS
-96 -97 -98
PIN (dBm)
-99
-100 -101 -102
Figure 5: Worst Case RSSI Response Time
Figure 6: BER vs. Input Power (typical)
Page 3
PIN ASSIGNMENTS
Pinned Receiver
Pin #
11 CS1 / SS CLOCK
12 CS2 / SS DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
ANT
GND
GND
GND
GND
GND
GND
GND
NC
CS0
CS1 / SS CLOCK
CS2 / SS DATA
PDN
RSSI
MODE
VCC
AUDIO
DATA
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PIN DESCRIPTIONS
Surface-Mount Receiver
1
ANT
Name
Equivalent Circuit
Description
RF In
50Ω
50-ohm RF Input
17 AUDIO
18 DATA
15 MODE
16 VCC
13 PDN
14 RSSI
1 ANT
2 GND
3 GND
4 GND
5 GND
6 GND
7 GND
8 GND
9
N/C
10 CS0
2-8
9
10
GND
NC
CS0
Analog Ground
No Connection
25k
Channel Select 0
CS0
11
CS1 /
SS CLOCK
µ
25k
CS1
12
CS2 /
SS DATA
µ
Channel Select 1 /
Serial Select Clock
25k
Figure 7: HP3 Series Receiver Pinout
CS2
µ
Channel Select 2 /
Serial Select Data
V
CC
Pin #
1
2-8
9
10
11
CS2 / SS
DATA
PDN
CS1 / SS
CLOCK
CS0
NC
No Connection
Channel Select 0
GND
Analog Ground
ANT
50-ohm RF Input
Name
Description
13
PDN
470k
PDN
Power Down
(Active Low)
RSSI
14
RSSI
12
13
14
RSSI
Channel Select 1 / Serial Select Clock. Channel Select 1
when in parallel channel selection mode, clock input for
serial channel selection mode.
Channel Select 1 / Serial Select Data. Channel Select 2
when in parallel channel selection mode, data input for
serial channel selection mode.
Power Down. Pulling this line low will place the receiver
into a low-current state. The module will not be able to
receive a signal in this state.
Received Signal Strength Indicator. This line will supply an
analog voltage that is proportional to the strength of the
received signal.
Mode Select. GND for parallel channel selection, V
CC
for
serial channel selection
Received Signal
Strength Indicator
15
MODE
25k
Mode Select
µ
16
V
CC
V
CC
Voltage Input 2.8-13V
17
AUDIO
1V
P-P
Analog Output
15
16
17
18
19-36
Page 4
MODE
V
CC
AUDIO
DATA
NC
4.7k
Supply Voltage
Recovered Analog Output
Digital Data Output. This line will output the demodulated
digital data.
No Connection (SMD only)
18
DATA
Digital Data Output
19-36
NC
SMD Only
No Connection
Figure 8: Pin Functions and Equivalent Circuits
Page 5
THEORY OF OPERATION
The HP3 is a high-performance multi-channel, dual-conversion superhet
receiver capable of recovering both analog (FM) and digital (FSK) information
from a matching HP Series transmitter. FM / FSK modulation offers significant
advantages over AM or OOK modulation methods, including increased noise
immunity and the receiver’s ability to capture in the presence of multiple signals.
This is especially helpful in crowded bands, like that in which the HP3 operates.
MODE
CS0
Channel
CS1
Select
CS2
POWER-UP SEQUENCE
As previously mentioned, the HP3 is controlled
by an on-board microprocessor. When power
is applied, the microprocessor executes the
receiver start-up sequence, after which the
receiver is ready to receive valid data.
POWER ON
Squelch Data
Output Pin
Parallel Mode
Determine Mode
Serial Mode
{
4MHz
Int. Osc.
PLL
RSSI
10.7MHz
BPF
VCO
Quad
34.7M
BPF
LNA
10.7M
BPF
IF
Amp
24MHz
Crystal
The adjacent figure shows the start-up
sequence. This sequence is executed when
power is applied to the V
CC
line or when the
PDN line is taken high.
Read Channel
Selection Inputs
Program Freq. Synth
To Default CH. 50
Program Frequency
Synthesizer
Crystal Oscillator
Begins to Operate
Digital
Data
Analog
Data
SAW BPF
On power-up, the microprocessor reads the
external channel selection lines and sets the
frequency synthesizer to the appropriate
channel. Once the frequency synthesizer has
stabilized, the receiver is ready to accept data.
Crystal Oscillator
Begins to Work
Ready for
Serial Data Input
Determine Squelch
State Data Output Pin
Determine Squelch
State Data Output Pin
Cycle Here Until
Channel
or Mode Change
Cycle Here Until More
Data Input
or Mode Change
Limiter
10.7M
Discriminator
Figure 10: Start-Up Sequence
Figure 9: HP3 Series Receiver Block Diagram
POWER SUPPLY
Once filtered, the signal is amplified by a Low Noise Amplifier (LNA) to increase
the receiver sensitivity and lower the overall noise figure of the receiver. After the
LNA, the signal is mixed with a synthesized local oscillator operating 34.7MHz
below the incoming transmission frequency to produce the first Intermediate
Frequency (IF).
The second conversion and FM demodulation is achieved by a high-
performance IF strip that mixes the 34.7MHz first conversion frequency with
24.0MHz from a precision crystal oscillator. The resulting second IF of 10.7MHz
is then highly amplified in preparation for demodulation.
A quadrature demodulator is used to recover the baseband signal from the
carrier. The demodulated waveform is filtered, after which it closely resembles
the original signal. The signal is routed to the analog output pin and the data
slicer stage, which provides squared digital output via the data output pin. A key
feature of the HP3 is the transparency of its digital output, which does not impose
balancing or duty-cycle requirements within a range of 100bps to 56kbps.
An on-board microcontroller manages receiver functions and greatly simplifies
user interface. The microcontroller reads the channel selection lines and
programs the on-board synthesizer. This frees the designer from complex
programming requirements and allows for manual or software channel selection.
The microcontroller also monitors incoming signal strength and squelches the
data output when the signal is not strong enough for accurate data detection.
A 10Ω resistor in series with the supply followed by a
Figure 11: Supply Filter
10µF tantalum capacitor from V
CC
to ground will help in cases where the quality
of supply power is poor. This filter should be placed close to the module’s supply
lines. These values may need to be adjusted depending on the noise present on
the supply line.
USING THE PDN PIN
The Power Down (PDN) line can be used to power down the receiver without the
need for an external switch. This line has an internal pull-up, so when it is held
high or simply left floating, the module will be active.
When the PDN line is pulled to ground, the receiver will enter into a low-current
(<10µA) power-down mode. During this time the receiver is off and cannot
perform any function. It may be useful to note that the startup time coming out
of power-down will be slightly less than when applying V
CC
.
The PDN line allows easy control of the receiver state from external
components, like a microcontroller. By periodically activating the receiver,
checking for data, then powering down, the receiver’s average current
consumption can be greatly reduced, saving power in battery-operated
applications.
Page 6
+
The single-ended RF port is matched to 50-ohms to support commonly available
antennas, such as those manufactured by Linx. The RF signal coming in from
the antenna is filtered by a Surface Acoustic Wave (SAW) filter to attenuate
unwanted RF energy. A SAW filter provides significantly higher performance
than other filter types, such as an LC bandpass filter.
The HP3 incorporates a precision, low-dropout
regulator on-board, which allows operation over an
input voltage range of 2.8 to 13 volts DC. Despite this
regulator, it is still important to provide a supply that
is free of noise. Power supply noise can significantly
affect the receiver sensitivity; therefore, providing a
clean power supply for the module should be a high
priority during design.
Vcc TO
MODULE
10Ω
Vcc IN
10μF
Page 7
THE DATA OUTPUT
The DATA line outputs recovered digital data. It is an open collector output with
an internal 4.7kΩ pull-up. When an RF transmission is not present, or when the
received signal strength is too low to ensure proper demodulation, the data
output is squelched continuous high. This feature supports direct operation with
UARTs, which require their input to be continuously high. An HP3 transmitter and
receiver can be directly connected between two UARTs without the need for
buffering or logical inversion. It should be noted that the squelch level is set just
over the receiver’s internal noise threshold. Any external RF activity above that
threshold will “break squelch” and produce hashing on the line. While the DATA
line will be reliably squelched in low-noise environments, the designer should
always plan for the potential of hashing.
Parameter
T1
T2
T3
T4
TIMING CONSIDERATIONS
There are four major timing considerations to be aware of when designing with
the HP3 Series receiver. These are shown in the table below.
Description
Max.
Time between DATA output transitions
20.0mS
Channel change time (time to valid data)
1.5mS
Receiver turn-on time via PDN
Receiver turn-on time via V
CC
3.0mS
7.0mS
AUDIO OUTPUT
The HP3 Series is optimized for the transmission of serial data; however, it can
also be used very effectively to send a variety of analog signals, including audio.
The ability of the HP3 to send combinations of audio and data opens new areas
of opportunity for creative design.
The analog output of the AUDIO line is valid from 50 Hz to 28 kHz, providing an
AC signal of about 1V peak-to-peak. This is a high impedance output and not
suitable for directly driving low-impedance loads, such as a speaker. In
applications where a low impedance load is to be driven, a buffer circuit should
always be used. For example, in the case of a speaker, a simple op-amp circuit
such as the one shown below can be used to act as an impedance converter.
VCC
T1 is the maximum amount of time that can elapse without a data transition. Data
must always be considered in both the analog and the digital domain. Because
the data stream is asynchronous and no particular format is imposed, it is
possible for the data to meet the receiver’s data rate requirement yet violate the
analog frequency requirements. For example, if a 255 (0FF hex) were sent
continuously, the receiver would view the data as a DC level. It would hold that
level until a transition was required to meet the minimum frequency specification.
If no transition occurred, data integrity could not be guaranteed. While no
particular structure or balancing requirement is imposed, the designer must
ensure that both analog and digital signals meet the transition specification.
T2 is the worst-case time needed for a powered-up module to switch between
channels after a valid channel selection. This time does not include external
overhead for loading a desired channel in the serial channel-selection mode.
T3 is the time to receiver readiness from the PDN line going high. Receiver
readiness is determined by valid data on the DATA line. This assumes an
incoming data stream and the presence of stable supply on V
CC
.
1uF
HP Analog Out
–
5
4
+
10k
3
2
6
T4 is the time to receiver readiness from the application of V
CC
. Receiver
readiness is determined by valid data on the DATA line. This assumes an
incoming data stream and the PDN line is high or open.
250uF
0.05uF
LM386
10 ohm
RECEIVING DATA
Once an RF link has been established, the challenge becomes how to effectively
transfer data across it. While a properly designed RF link provides reliable data
transfer under most conditions, there are still distinct differences from a wired link
that must be addressed. Since the modules do not incorporate internal encoding
or decoding, the user has tremendous flexibility in how data is handled.
Figure 12: Audio Buffer Amplifier
The transmitter’s modulation voltage is critical, since it determines the carrier
deviation and distortion. The transmitter input level should be adjusted to
achieve the optimum results for your application in your circuit. Please refer to
the transmitter data guide for full details.
When used for audio, the analog output of the receiver should be filtered and
buffered to obtain maximum sound quality. For voice, a 3-4kHz low-pass filter is
often employed. For broader-range sources, such as music, a 12-17kHz cutoff
may be more appropriate. In applications that require high-quality audio, a
compandor may be used to further improve SNR. The HP3 is capable of
providing audio quality comparable to a radio or intercom. For applications where
true high fidelity audio is required, the HP3 will probably not be the best choice,
and a device optimized for audio should be utilized.
Page 8
It is important to separate the types of transmissions that are technically possible
from those that are legally allowed in the country of operation. Application Notes
AN-00126, AN-00140 and Part 15, Section 249 of the FCC rules should be
reviewed for details on acceptable transmission content in the U.S.
If you want to transfer simple control or status signals (such as button presses)
and your product does not have a microprocessor or you wish to avoid protocol
development, consider using an encoder / decoder IC set. These chips are
available from several manufacturers, including Linx. They take care of all
encoding and decoding functions and provide a number of data lines to which
switches can be directly connected. Address bits are usually provided for
security and to allow the addressing of multiple receivers independently. These
ICs are an excellent way to bring basic remote control products to market quickly
and inexpensively. It is also a simple task to interface with inexpensive
microprocessors or one of many IR, remote control, DTMF, or modem ICs.
Page 9
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