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74AUPG04GTR

Description
Low power single inverter gate
Categorylogic    logic   
File Size369KB,18 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric Compare View All

74AUPG04GTR Overview

Low power single inverter gate

74AUPG04GTR Parametric

Parameter NameAttribute value
MakerSTMicroelectronics
Parts packaging codeSOT
package instruction1.60 X 1.60 MM, ROHS COMPLIANT, SOT-665, 5 PIN
Contacts5
Manufacturer packaging codeSOT665
Reach Compliance Codeunknow
seriesAUP/ULP/V
JESD-30 codeR-PDSO-F5
length1.6 mm
Logic integrated circuit typeINVERTER
Number of functions1
Number of entries1
Number of terminals5
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeVSOF
Package shapeRECTANGULAR
Package formSMALL OUTLINE, VERY THIN PROFILE
propagation delay (tpd)16 ns
Certification statusNot Qualified
Maximum seat height0.6 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)1.2 V
Nominal supply voltage (Vsup)2.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formFLAT
Terminal pitch0.5 mm
Terminal locationDUAL
width1.2 mm
74AUP1G04
Low power single inverter gate
Features
High speed: t
PD
= 4.3 ns (max.) at V
CC
= 2.3 V
Power down protection on inputs and outputs
Balanced propagation delays:
t
PLH
t
PHL
Operating voltage range:
V
CC
(opr) = 1.2 to 3.6 V
Low power dissipation:
I
CC
= 1 µA (max.) at T
A
= 85 °C
Latch-up performance exceeds 300 mA (JESD
78, Class II)
ESD performance:
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SOT-665
DFN6L
Applications
Mobile phones
Personal digital assistants (PDAs)
Description
The 74AUP1G04 is a low voltage CMOS single
inverter gate fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for 1.2 to 3.6 V operations
and low power and low noise applications.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
Table 1.
Device summary
Order code
74AUPG04DTR
74AUPG04GTR
Package
DFN6L (1.2 x 1 mm)
SOT-665 (1.6 x 1.6 mm)
Packing
Tape and reel
Tape and reel
March 2008
Rev 1
1/18
www.st.com
18

74AUPG04GTR Related Products

74AUPG04GTR 74AUP1G04 74AUPG04DTR
Description Low power single inverter gate Low power single inverter gate Low power single inverter gate
Maker STMicroelectronics - STMicroelectronics
Parts packaging code SOT - DFN
package instruction 1.60 X 1.60 MM, ROHS COMPLIANT, SOT-665, 5 PIN - VSON,
Contacts 5 - 6
Reach Compliance Code unknow - unknow
series AUP/ULP/V - AUP/ULP/V
JESD-30 code R-PDSO-F5 - R-XDSO-N6
length 1.6 mm - 1.2 mm
Logic integrated circuit type INVERTER - INVERTER
Number of functions 1 - 1
Number of entries 1 - 1
Number of terminals 5 - 6
Maximum operating temperature 85 °C - 85 °C
Minimum operating temperature -40 °C - -40 °C
Package body material PLASTIC/EPOXY - UNSPECIFIED
encapsulated code VSOF - VSON
Package shape RECTANGULAR - RECTANGULAR
Package form SMALL OUTLINE, VERY THIN PROFILE - SMALL OUTLINE, VERY THIN PROFILE
propagation delay (tpd) 16 ns - 16 ns
Certification status Not Qualified - Not Qualified
Maximum seat height 0.6 mm - 0.55 mm
Maximum supply voltage (Vsup) 3.6 V - 3.6 V
Minimum supply voltage (Vsup) 1.2 V - 1.2 V
Nominal supply voltage (Vsup) 2.3 V - 2.3 V
surface mount YES - YES
technology CMOS - CMOS
Temperature level INDUSTRIAL - INDUSTRIAL
Terminal form FLAT - NO LEAD
Terminal pitch 0.5 mm - 0.4 mm
Terminal location DUAL - DUAL
width 1.2 mm - 1 mm
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