74AUP1G04 datasheet, PDF - EEWORLD Datasheet

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74AUP1G04: DescriptionLow power single inverter gate; File Size369KB，18 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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74AUP1G04 Overview

Low power single inverter gate

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74AUP1G04

Low power single inverter gate

Features

■

High speed: t

= 4.3 ns (max.) at V

= 2.3 V

Power down protection on inputs and outputs

Balanced propagation delays:

PLH

≈

PHL

Operating voltage range:

(opr) = 1.2 to 3.6 V

Low power dissipation:

= 1 µA (max.) at T

= 85 °C

Latch-up performance exceeds 300 mA (JESD

78, Class II)

ESD performance:

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

SOT-665

DFN6L

Applications

■

Mobile phones

Personal digital assistants (PDAs)

Description

The 74AUP1G04 is a low voltage CMOS single

inverter gate fabricated with sub-micron silicon

gate and double-layer metal wiring C

MOS

technology. It is ideal for 1.2 to 3.6 V operations

and low power and low noise applications.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2kV ESD immunity and transient excess

voltage.

Table 1.

Device summary

Order code

74AUPG04DTR

74AUPG04GTR

Package

DFN6L (1.2 x 1 mm)

SOT-665 (1.6 x 1.6 mm)

Packing

Tape and reel

March 2008

Rev 1

1/18

www.st.com

74AUP1G04 Related Products

	74AUP1G04	74AUPG04DTR	74AUPG04GTR
Description	Low power single inverter gate	Low power single inverter gate	Low power single inverter gate
Maker	-	STMicroelectronics	STMicroelectronics
Parts packaging code	-	DFN	SOT
package instruction	-	VSON,	1.60 X 1.60 MM, ROHS COMPLIANT, SOT-665, 5 PIN
Contacts	-	6	5
Reach Compliance Code	-	unknow	unknow
series	-	AUP/ULP/V	AUP/ULP/V
JESD-30 code	-	R-XDSO-N6	R-PDSO-F5
length	-	1.2 mm	1.6 mm
Logic integrated circuit type	-	INVERTER	INVERTER
Number of functions	-	1	1
Number of entries	-	1	1
Number of terminals	-	6	5
Maximum operating temperature	-	85 °C	85 °C
Minimum operating temperature	-	-40 °C	-40 °C
Package body material	-	UNSPECIFIED	PLASTIC/EPOXY
encapsulated code	-	VSON	VSOF
Package shape	-	RECTANGULAR	RECTANGULAR
Package form	-	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE
propagation delay (tpd)	-	16 ns	16 ns
Certification status	-	Not Qualified	Not Qualified
Maximum seat height	-	0.55 mm	0.6 mm
Maximum supply voltage (Vsup)	-	3.6 V	3.6 V
Minimum supply voltage (Vsup)	-	1.2 V	1.2 V
Nominal supply voltage (Vsup)	-	2.3 V	2.3 V
surface mount	-	YES	YES
technology	-	CMOS	CMOS
Temperature level	-	INDUSTRIAL	INDUSTRIAL
Terminal form	-	NO LEAD	FLAT
Terminal pitch	-	0.4 mm	0.5 mm
Terminal location	-	DUAL	DUAL
width	-	1 mm	1.2 mm

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