M54HC109_04 datasheet, PDF - EEWORLD Datasheet

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M54HC109_04: DescriptionRAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR; File Size177KB，10 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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M54HC109_04 Overview

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

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M54HC109

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

HIGH SPEED :

MAX

= 67MHz (TYP.) at V

= 6V

LOW POWER DISSIPATION:

=2µA(MAX.) at T

=25°C

HIGH NOISE IMMUNITY:

NIH

= V

NIL

= 28 % V

(MIN.)

SYMMETRICAL OUTPUT IMPEDANCE:

| = I

= 4mA (MIN)

BALANCED PROPAGATION DELAYS:

PLH

≅

PHL

WIDE OPERATING VOLTAGE RANGE:

(OPR) = 2V to 6V

PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 109

SPACE GRADE-1: ESA SCC QUALIFIED

50 krad QUALIFIED, 100 krad AVAILABLE ON

REQUEST

NO SEL UNDER HIGH LET HEAVY IONS

IRRADIATION

DEVICE FULLY COMPLIANT WITH

SCC-9306-048

DILC-16

FPC-16

ORDER CODES

PACKAGE

DILC

FPC

M54HC109D

M54HC109K

M54HC109D1

M54HC109K1

DESCRIPTION

The M54HC109 is an high speed CMOS DUAL

J-K FLIP FLOP WITH PRESET AND CLEAR

fabricated with silicon gate C

MOS technology. In

accordance with the logic level on the J and K

input this device changes state on positive going

transition of the clock pulse. CLEAR and PRESET

are independent of the clock and are

accomplished by a logic low on the corresponding

input.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION

March 2004

1/10

M54HC109_04 Related Products

	M54HC109_04	M54HC109	M54HC109K	M54HC109D	M54HC109D1	M54HC109K1
Description	RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR	RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR	RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR	RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR	RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR	RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
Is it Rohs certified?	-	-	incompatible	incompatible	incompatible	incompatible
Maker	-	-	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics
Parts packaging code	-	-	DFP	DIP	DIP	DFP
package instruction	-	-	DFP, FL16,.3	CERAMIC, DIP-16	DIP, DIP16,.3	DFP, FL16,.3
Contacts	-	-	16	16	16	16
Reach Compliance Code	-	-	_compli	_compli	_compli	_compli
series	-	-	HC/UH	HC/UH	HC/UH	HC/UH
JESD-30 code	-	-	R-CDFP-F16	R-CDIP-T16	R-CDIP-T16	R-CDFP-F16
JESD-609 code	-	-	e0	e0	e0	e0
length	-	-	9.94 mm	20.32 mm	20.32 mm	9.94 mm
Load capacitance (CL)	-	-	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	-	-	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP
Maximum Frequency@Nom-Su	-	-	21000000 Hz	21000000 Hz	21000000 Hz	21000000 Hz
MaximumI(ol)	-	-	0.004 A	0.004 A	0.004 A	0.004 A
Number of digits	-	-	2	2	2	2
Number of functions	-	-	2	2	2	2
Number of terminals	-	-	16	16	16	16
Maximum operating temperature	-	-	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-	-	-55 °C	-55 °C	-55 °C	-55 °C
Output polarity	-	-	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	-	-	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	-	-	DFP	DIP	DIP	DFP
Encapsulate equivalent code	-	-	FL16,.3	DIP16,.3	DIP16,.3	FL16,.3
Package shape	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	-	-	FLATPACK	IN-LINE	IN-LINE	FLATPACK
Peak Reflow Temperature (Celsius)	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	-	-	2/6 V	2/6 V	2/6 V	2/6 V
Prop。Delay @ Nom-Su	-	-	45 ns	45 ns	45 ns	45 ns
propagation delay (tpd)	-	-	225 ns	225 ns	225 ns	225 ns
Certification status	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	-	2.38 mm	3.83 mm	3.83 mm	2.38 mm
Maximum supply voltage (Vsup)	-	-	6 V	6 V	6 V	6 V
Minimum supply voltage (Vsup)	-	-	2 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	-	-	4.5 V	4.5 V	4.5 V	4.5 V
surface mount	-	-	YES	NO	NO	YES
technology	-	-	CMOS	CMOS	CMOS	CMOS
Temperature level	-	-	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	-	-	FLAT	THROUGH-HOLE	THROUGH-HOLE	FLAT
Terminal pitch	-	-	1.27 mm	2.54 mm	2.54 mm	1.27 mm
Terminal location	-	-	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
total dose	-	-	50k Rad(Si) V	50k Rad(Si) V	50k Rad(Si) V	50k Rad(Si) V
Trigger type	-	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	-	-	6.91 mm	7.62 mm	7.62 mm	6.91 mm
minfmax	-	-	25 MHz	25 MHz	25 MHz	25 MHz

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