M54HC109
RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED :
f
MAX
= 67MHz (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
=2µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 109
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9306-048
DILC-16
FPC-16
ORDER CODES
PACKAGE
DILC
FPC
FM
M54HC109D
M54HC109K
EM
M54HC109D1
M54HC109K1
DESCRIPTION
The M54HC109 is an high speed CMOS DUAL
J-K FLIP FLOP WITH PRESET AND CLEAR
fabricated with silicon gate C
2
MOS technology. In
accordance with the logic level on the J and K
input this device changes state on positive going
transition of the clock pulse. CLEAR and PRESET
are independent of the clock and are
accomplished by a logic low on the corresponding
input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
March 2004
1/10
M54HC109
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
25
±
50
300
-65 to +150
265
Unit
V
V
V
mA
mA
mA
mA
mW
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
P
D
Power Dissipation
T
stg
T
L
Storage Temperature
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
t
r
, t
f
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
V
CC
= 2.0V
V
CC
= 4.5V
V
CC
= 6.0V
Parameter
Value
2 to 6
0 to V
CC
0 to V
CC
-55 to 125
0 to 1000
0 to 500
0 to 400
Unit
V
V
V
°C
ns
ns
ns
3/10
M54HC109
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
T
A
= 25°C
Min.
Typ.
30
8
7
50
16
13
50
16
13
17
59
67
15
6
6
15
6
6
17
5
4
Max.
75
15
13
150
30
26
150
30
26
5
25
30
75
15
13
75
15
13
75
15
13
0
0
0
50
10
9
95
19
16
95
19
16
95
19
16
0
0
0
65
13
11
Value
-40 to 85°C
Min.
Max.
95
19
16
190
38
32
190
38
32
4.2
21
25
110
22
19
110
22
19
110
22
19
0
0
0
75
15
13
-55 to 125°C
Min.
Max.
110
22
19
225
45
38
225
45
38
ns
Unit
t
TLH
t
THL
Output Transition
Time
t
PLH
t
PHL
Propagation Delay
Time (CK - Q, Q)
t
PLH
t
PHL
Propagation Delay
Time (CLR, PR -
Q, Q)
f
MAX
Maximum Clock
Frequency
Minimum Pulse
Width (CK)
Minimum Pulse
Width (CLR, PR)
Minimum Set-Up
Time
Minimum Hold
Time
Minimum Removal
Time (CLR, PR)
ns
ns
6.2
31
37
MHz
t
W(H)
t
W(L)
t
W(L)
ns
ns
t
s
ns
t
h
ns
t
REM
13
4
3
ns
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
5.0
T
A
= 25°C
Min.
Typ.
5
41
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per FLIP/
FLOP)
5/10
Embedded System
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