FAN7382 High- and Low-Side Gate Driver
February 2007
FAN7382
High- and Low-Side Gate Driver
Features
Floating Channels Designed for Bootstrap Operation
to +600V
Typically 350mA/650mA Sourcing/Sinking Current
Driving Capability for Both Channels
Common-Mode dv/dt Noise Canceling Circuit
Extended Allowable Negative V
S
Swing to -9.8V for
Signal Propagation at V
CC
=V
BS
=15V
V
CC
& V
BS
Supply Range from 10V to 20V
UVLO Functions for Both Channels
TTL Compatible Input Logic Threshold Levels
Matched Propagation Delay Below 50nsec
Output In-phase with Input Signal
Description
The FAN7382, a monolithic high and low side gate-drive
IC, can drive MOSFETs and IGBTs that operate up to
+600V. Fairchild’s high-voltage process and common-
mode noise canceling technique provides stable opera-
tion of the high-side driver under high-dv/dt noise circum-
stances. An advanced level-shift circuit allows high-side
gate driver operation up to V
S
=-9.8V (typical) for
V
BS
=15V. The input logic level is compatible with stan-
dard TTL-series logic gates. UVLO circuits for both chan-
nels prevent malfunction when V
CC
or V
BS
is lower than
the specified threshold voltage. Output drivers typically
source/sink 350mA/650mA, respectively, which is suit-
able for fluorescent lamp ballasts, PDP scan drivers,
motor controls, etc.
Applications
PDP Scan Driver
Fluorescent Lamp Ballast
SMPS
Motor Driver
8-SOP
8-DIP
14-SOP
Ordering Information
Part Number
FAN7382N
FAN7382M
(1)
FAN7382MX
(1)
FAN7382M1
(1)
FAN7382M1X
(1)
Note:
1. These devices passed wave soldering test by JESD22A-111.
Package
8-DIP
8-SOP
14-SOP
Pb-Free
Operating Temperature Range
Packing Method
Tube
Tube
Yes
-40°C ~ 125°C
Tape & Reel
Tube
Tape & Reel
© 2005 Fairchild Semiconductor Corporation
FAN7382 Rev. 1.0.8
www.fairchildsemi.com
FAN7382 High- and Low-Side Gate Driver
Typical Application Circuit
15V
R
BOOT
D
BOOT
600V
1 V
CC
2
V
B
8
Q1
HO 7
C
BOOT
V
S
6
Q2
R3
R1
R2
HIN
LIN
C1
HIN
3 LIN
4 COM
LO 5
Load
R4
FAN7382 Rev.05
Figure 1. Application Circuit for Half-Bridge
Internal Block Diagram
8
UVLO
V
B
DRIVER
7
PULSE
GENERATOR
HO
HIN
2
500K
HS(ON/OFF)
NOISE
CANCELLER
R
S
R
Q
6
V
S
UVLO
1
DRIVER
V
CC
LS(ON/OFF)
LIN
3
500K
DELAY
5
LO
4
COM
FAN7382 Rev.04
Figure 2. Functional Block Diagram
© 2005 Fairchild Semiconductor Corporation
FAN7382 Rev. 1.0.8
2
www.fairchildsemi.com
FAN7382 High- and Low-Side Gate Driver
Pin Assignments
FAN7382N
FAN7382M
V
CC
HIN
LIN
COM
1
2
3
4
8
7
6
5
FAN7382M1
V
B
HO
V
S
LO
V
CC
HIN
LIN
NC
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
V
B
HO
V
S
NC
NC
NC
FAN7382 Rev.05
COM
LO
FAN7382 Rev.01
Figure 3. Pin Configuration (Top View)
Pin Definitions
Name
V
CC
HIN
LIN
COM
LO
V
S
HO
V
B
Low-Side Supply Voltage
Logic Input for High-Side Gate Driver Output
Logic Input for Low-Side Gate Driver Output
Logic Ground and Low-Side Driver Return
Low-Side Driver Output
High-Voltage Floating Supply Return
High-Side Driver Output
High-Side Floating Supply
Description
© 2005 Fairchild Semiconductor Corporation
FAN7382 Rev. 1.0.8
3
www.fairchildsemi.com
FAN7382 High- and Low-Side Gate Driver
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
V
S
V
B
V
HO
V
CC
V
LO
V
IN
COM
dV
S
/dt
P
D(2)(3)(4)
Characteristics
High-side offset voltage
High-side floating supply voltage
High-side floating output voltage HO
Low-side and logic fixed supply voltage
Low-side output voltage LO
Logic input voltage (HIN, LIN)
Logic ground
Allowable offset voltage slew rate
Min.
V
B
-25
-0.3
V
S
-0.3
-0.3
-0.3
-0.3
V
CC
-25
8-SOP
Max.
V
B
+0.3
625
V
B
+0.3
25
V
CC
+0.3
V
CC
+0.3
V
CC
+0.3
50
0.625
1.0
1.2
200
110
100
150
150
Unit
V
V/ns
W
Power dissipation
14-SOP
8-DIP
8-SOP
θ
JA
T
J
T
STG
Notes:
Thermal resistance, junction-to-ambient
Junction temperature
Storage temperature
14-SOP
8-DIP
°C/W
°C
°C
2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
3. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
4. Do not exceed P
D
under any circumstances.
Recommended Operating Ratings
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
B
V
S
V
HO
V
LO
V
IN
V
CC
T
A
Parameter
High-side floating supply voltage
High-side floating supply offset voltage
High-side (HO) output voltage
Low-side (LO) output voltage
Logic input voltage (HIN, LIN)
Low-side supply voltage
Ambient temperature
Min.
V
S
+10
6-V
CC
V
S
COM
COM
10
-40
Max.
V
S
+20
600
V
B
V
CC
V
CC
20
125
Unit
V
°C
© 2005 Fairchild Semiconductor Corporation
FAN7382 Rev. 1.0.8
4
www.fairchildsemi.com
FAN7382 High- and Low-Side Gate Driver
Electrical Characteristics
V
BIAS
(V
CC
, V
BS
)=15.0V, T
A
= 25°C, unless otherwise specified. The V
IN
and I
IN
parameters are referenced to COM.
The V
O
and I
O
parameters are referenced to V
S
and COM and are applicable to the respective outputs HO and LO.
Symbol
V
CCUV+
V
BSUV+
V
CCUV-
V
BSUV-
Characteristics
V
CC
and V
BS
supply under-voltage
positive going threshold
V
CC
and V
BS
supply under-voltage
negative going threshold
Test Condition
Min.
8.2
7.6
Typ. Max.
9.2
8.7
0.6
10.0
9.6
Unit
V
V
CCUVH
V
CC
supply under-voltage lockout
V
BSUVH
hysteresis
I
LK
I
QBS
I
QCC
I
PBS
I
PCC
V
IH
V
IL
V
OH
V
OL
I
IN+
I
IN-
I
O+
I
O-
V
S
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Operating V
BS
supply current
Operating V
CC
supply current
Logic "1" input voltage
Logic "0" input voltage
High-level output voltage, V
BIAS
-V
O
Low-level output voltage, V
O
Logic "1" input bias current
Logic "0" input bias current
Output high short-circuit pulsed current
Output low short-circuit pulsed current
Allowable negative V
S
pin voltage for
HIN signal propagation to HO
I
O
=20mA
V
IN
=5V
V
IN
=0V
V
O
=0V, V
IN
=5V with PW<10µs
V
O
=15V, V
IN
=0V with PW<10µs
250
500
V
B
=V
S
=600V
V
IN
=0V or 5V
V
IN
=0V or 5V
f
IN
=20kHz,rms value
f
IN
=20kHz,rms value
2.9
50
45
70
120
180
600
600
0.8
1.0
0.6
10
1.0
350
650
-9.8
-7.0
20
2.0
µA
mA
V
µA
µA
V
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
)=15.0V, V
S
=COM, C
L
=1000pF and, T
A
= 25°C, unless otherwise specified.
Symbol
t
on
t
off
t
r
t
f
MT
Note:
Characteristics
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
Delay matching, HS & LS turn-on/off
Test Condition
V
S
=0V
V
S
=0V or 600V
(5)
Min.
100
100
20
Typ.
170
200
60
30
Max.
300
300
140
80
50
Unit
ns
5. This parameter guaranteed by design.
© 2005 Fairchild Semiconductor Corporation
FAN7382 Rev. 1.0.8
5
www.fairchildsemi.com
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