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71T75802S150BGG8

Description
PBGA-119, Reel
Categorystorage    storage   
File Size355KB,27 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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71T75802S150BGG8 Overview

PBGA-119, Reel

71T75802S150BGG8 Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codePBGA
package instructionBGA, BGA119,7X17,50
Contacts119
Manufacturer packaging codeBGG119
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time3.8 ns
Other featuresPIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)150 MHz
I/O typeCOMMON
JESD-30 codeR-PBGA-B119
JESD-609 codee1
length22 mm
memory density18874368 bit
Memory IC TypeZBT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of terminals119
word count1048576 words
character code1000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize1MX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA119,7X17,50
Package shapeRECTANGULAR
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply2.5 V
Certification statusNot Qualified
Maximum seat height2.36 mm
Maximum standby current0.04 A
Minimum standby current2.38 V
Maximum slew rate0.215 mA
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
Base Number Matches1
512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
IDT71T75602
IDT71T75802
Features
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V I/O Supply (V
DDQ
)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Green parts available, see Ordering Information
Functional Block Diagram - 512K x 36
LBO
512Kx36 BIT
MEMORY ARRAY
Address
Address A [0:18]
CE1
,
CE2
,
CE2
R
/
W
CEN
ADV/LD
BW
x
D
Q
D
Q
Control
DI
DO
D
Input Register
Q
Clk
Control Logic
Mux
Sel
Clock
D
Output Register
Q
OE
Gate
Clk
TMS
TDI
TCK
TRST
(optional)
JTAG
TDO
Data I/O [0:31],
I/O P[1:4]
5313 drw 01
OCTOBER 2017
1
©2017 Integrated Device Technology, Inc.
DSC-5313/11
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