Freescale Semiconductor
Advance Information
Document Number: MC33742
Rev. 11, 6/2008
System Basis Chip with
Enhanced High Speed CAN
Transceiver
The 33742 and the 33742S are SPI-controlled System Basis Chips
(SBCs) combining many frequently used functions along with a CAN 2.0-
compliant transceiver, used in many automotive electronic control units
(ECUs). The 33742 SBC has a fully protected fixed 5.0V low dropout
internal regulator with current limiting, over-temperature pre-warning,
and reset. A second 5.0V regulator can be implemented using external
pass PNP bipolar junction pass transistor driven by the SBC’s external
V2 sense input and V2 output drive pins.
The SBC has four main operating modes: Normal, Standby, Stop, and
Sleep mode. Additionally there is an internally switched high side power
supply output, four wake-up inputs pins, a programmable window
watchdog, interrupt, reset, and a SPI module for communication and
control. The high speed CAN A and B transceiver is available for inter-
module communication.
Features
• 1.0Mbps CAN transceiver bus interface with bus diagnostic capability
• SPI control at frequencies up to 4.0Mhz
• 5.0V low dropout voltage regulator with current limiting, over-
temperature prewarning, and output monitoring and reset
• a Second 5.0V regulator capability using an external series pass
transistor
• Normal, Standby, Stop, and Sleep modes of operation with Low sleep
and Stop mode current
• A high side (HS) switch output driver for controlling external circuitry.
• Pb-free packaging designated by suffix code EG and EP
33742
33742S
SYSTEM BASIS CHIP
DW SUFFIX
EG SUFFIX (PB-FREE)
98ASB42345B
28-PIN SOICW
EP SUFFIX
(PB-FREE)
98ASA10825D
48-PIN QFN
ORDERING INFORMATION
Device
MC33742DW/R2
MCZ33742EG/R2
MC33742SDW/R2
MCZ33742SEG/R2
MC33742EP/R2
48 QFN
- 40°C to 125°C
28 SOICW
Temperature
Range (T
A
)
Package
V
PWR
33742
5.0V
VDD
VSUP
V2
MCU
CS
SCLK
MOSI
MISO
V2CTRL
RST
V2
CS
SCLK
MOSI
MISO
INT
TXD
L0
L1
L2
L3
WDOG
HS
Safe
Circuitry
ECU Local
Circuitry
Twisted
V
PWR
SPI
GND
CANH
RXD CANL
GND
Pair
CAN Bus
Figure 1. 33742 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Differences During a Reset Condition
Part No.
33742
Reset Duration
15ms (typical)
Device Differences
The duration the
RST
pin is asserted low when the Reset mode is entered after
the SBC is powered up, a V
DD
under-voltage condition is detected, and the
watchdog register is not properly triggered.
The duration the
RST
pin is asserted low when the Reset mode is entered after
the SBC is powered up, a V
DD
under-voltage condition is detected, and the
watchdog register is not properly triggered.
See Page
page
20
33742S
3.5ms (typical)
page
20
33742
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
V2CTRL
V2
VSUP Monitor
Dual Voltage Regulator
VSUP
V1 Monitor
5.0V/200mA
V1
HS Control
Mode Control
Oscillator
HS
Interrupt
Watchdog
Reset
INT
WDOG
RST
MOSI
SPI
SCLK
MISO
CS
L1
L2
L3
L4
Programmable
Wake-up Input
CANH
CANL
High-speed
1.0Mbps
CAN Physical
Interface
TXD
RXD
GND
Figure 2. 33742 Simplified Internal Block Diagram
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
RXD
TXD
VDD
RST
INT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WDOG
CS
GND
GND
GND
GND
V2
V2CTRL
VSUP
HS
L0
MOSI
MISO
SCLK
GND
GND
GND
GND
CANL
CANH
L3
L2
L1
Figure 3. 33742 28-Pin Connections
Table 2. 33742 28-Pin Definitions
A functional description of each pin can be found in the
Functional Pin description
section beginning on page
23.
Pin
1
2
3
4
5
6–9
20 – 23
10
11
12
13
14 –17
18
19
24
25
26
27
28
Pin Name
RXD
TXD
VDD
RST
INT
GND
V2
V2CTRL
VSUP
HS
L0- L3
CANH
CANL
SCLK
MISO
MOSI
CS
WDOG
Formal Name
Receive Data
Transmit Data
Voltage Digital Drain
Reset Output
(Active LOW)
Interrupt Output
(Active LOW)
Ground
Voltage Source 2
Voltage Source 2 Control
Voltage Supply
High Side Output
Level 0 - 3 Inputs
CAN High Output
CAN Low Output
Serial Data Clock
Master In Slave Out
Master Out Slave In
Chip Select
(Active LOW)
Watchdog Output
(Active LOW)
CAN bus receive data output pin.
CAN bus transmit data input pin.
Definition
5.0V regulator output pin. Supply pin for the MCU.
This is the device reset output pin whose main function is to reset the MCU. This pin has
an internal pullup current source to VDD.
This output is asserted LOW when an enabled interrupt condition occurs. The output is
a push-pull structure.
These device ground pins are internally connected to the package lead frame to provide
a 33742-to-PCB thermal path.
Sense input for the V2 regulator using an external series pass transistor. V2 is also the
internal supply for the CAN transceiver.
Output drive source for the V2 regulator connected to the external series pass transistor.
Supply input pin for the 33742.
Output of the internal high side switch. The output current is internally limited to 150mA.
Inputs from external switches or from logic circuitry.
CAN high output pin.
CAN low output pin.
Clock input pin for the Serial Peripheral Interface (SPI).
SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the high-
impedance state.
SPI data received by the 33742.
The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted
LOW, the 33742 is the selected device of the SPI bus.
The WDOG output pin is asserted LOW if the software watchdog is not correctly
triggered.
33742
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
48
47
46
45
44
43
42
41
40
39
38
37
NC
NC
NC
NC
GND
GND
GND
GND
NC
NC
NC
NC
Transparent
Top View
NC
SCLK
MISO
MOSI
CS
WDOG
RXD
TXD
VDD
RST
INT
NC
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
NC
CANL
CANH
L3
L2
L1
L0
HS
VSUP
V2 CTRL
V2
NC
Figure 4. 33742 48-Pin Connections
Table 3. 33742 48-Pin Definitions
A functional description of each pin can be found in the
Functional Pin description
section beginning on page
23.
Pin
1, 12-16,
21-25,
36-40,
45-48
2
3
4
5
6
7
8
9
10
11
17-20
41-44
Pin Name
NC
Formal Name
No Connect
No connection.
Definition
SCLK
MISO
MOSI
CS
WDOG
Serial Data Clock
Master In Slave Out
Master Out Slave In
Chip Select
(Active LOW)
Watchdog Output
(Active LOW)
Receive Data
Transmit Data
Voltage Digital Drain
Reset Output
(Active LOW)
Interrupt Output
(Active LOW)
Ground
RXD
TXD
VDD
RST
INT
GND
NC
NC
NC
NC
GND
GND
GND
GND
NC
NC
NC
NC
Clock input pin for the Serial Peripheral Interface (SPI).
SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the high-
impedance state.
SPI data received by the 33742.
The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted
LOW, the 33742 is the selected device of the SPI bus.
The WDOG output pin is asserted LOW if the software watchdog is not correctly
triggered.
CAN bus receive data output pin.
CAN bus transmit data input pin.
5.0V regulator output pin. Supply pin for the MCU.
This is the device reset output pin whose main function is to reset the MCU. This pin has
an internal pullup current source to VDD.
This output is asserted LOW when an enabled interrupt condition occurs. The output is
a push-pull structure.
These device ground pins are internally connected to the package lead frame to provide
a 33742-to-PCB thermal path.
13
14
15
16
17
18
19
20
21
22
23
24
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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