MC9S08LC60 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
•
•
•
•
40-MHz HCS08 CPU
HC08 instruction set with added BGND instruction
Background debugging system
Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
In-Circuit Emulator (ICE) debug module containing
two comparators and nine trigger modes. Eight deep
FIFO for storing change-of-flow addresses and
event-only data. ICE debug module supports both
tag and force breakpoints.
Support for up to 32 interrupt/reset sources
Peripherals
•
LCD
(liquid crystal display driver) — Compatible
with 5-V or 3-V LCD glass displays; functional in
wait and stop3 low-power modes; selectable
frontplane and backplane configurations:
–
–
•
4 x 40 or 3 x 41 (80-pin package)
4 x 32 or 3 x 33 (64-pin package)
•
•
•
Memory Options
•
Dual on-chip in-circuit programmable FLASH
memories with block protection and security
options; 60K and 36K options available
Program/erase of one FLASH array while executing
from another
On-chip random-access memory (RAM); 4K and
2.5K options available
•
•
•
•
•
•
Power-Saving Features
•
•
•
Wait plus three stops
Software disable of clock monitor and low-voltage
interrupt (LVI) for lowest stop current
Software-generated real-time clock (RTC) functions
using real-time interrupt (RTI)
•
ACMP
(analog comparator) — option to compare to
internal reference voltage; output is software
selectable to be driven to the input capture of TPM1
channel 0.
ADC
(analog-to-digital converter) — 8-channel,
12-bit with automatic compare function,
asynchronous clock source, temperature sensor and
internal bandgap reference channel. ADC is
hardware triggerable using the RTI counter.
SCI
(serial communications interface)
—
available
single-wire mode
SPI1
and
SPI2
— Two serial peripheral interface
modules
KBI
— Two 8-pin keyboard interrupt modules with
software selectable rising or falling edge detect
IIC
— Inter-integrated circuit bus module capable
of operation up to 100 kbps with maximum bus
loading; capable of higher baudrates with reduced
loading
TPM1
and
TPM2
— Two timer/pulse-width
modulators with selectable input capture, output
compare, and edge-aligned PWM capability on each
channel. Each timer module may be configured for
buffered, centered PWM (CPWM) on all channels.
Configurable Clock Source
•
Clock source options include crystal, resonator,
external clock, or internally generated clock with
precision nonvolatile memory (NVM) trimming
Automatic clock monitor function
Input/Output
•
Up to 24 general-purpose input/output (I/O) pins;
includes two output-only pins and one input-only
pin
Software selectable pullups on ports when used as
input. Selection is on an individual port bit basis.
Software selectable slew rate control on ports when
used as outputs (selection is on an individual port bit
basis)
Software selectable drive strength control on ports
when used as outputs (selection is on an individual
port bit basis)
Internal pullup on RESET and IRQ pin to reduce
customer system cost
•
•
•
System Protection
•
•
•
Optional computer operating properly (COP) reset
Low-voltage detection with reset or interrupt
Illegal opcode detection with reset
•
Package Options
•
•
•
64-pin low-profile quad flat package (LQFP)
80-pin LQFP
Power technology
京公网安备 11010802033920号
EEWORLD
