Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF52235DS
Rev. 7, 8/2008
MCF52235
MCF52235 ColdFire
Microcontroller Data Sheet
Supports MCF52230, MCF52231,
MCF52232, MCF52233, MCF52234,
MCF52235, and MCF52236
The MCF52235 is a member of the ColdFire
®
family of
reduced instruction set computing (RISC) microcontrollers.
This document provides an overview of the MCF52235
microcontroller family, focusing on its highly integrated and
diverse feature set.
This 32-bit device is based on the Version 2 ColdFire core
operating at a frequency up to 60 MHz, offering high
performance and low power consumption. On-chip memories
connected tightly to the processor core include up to 256
Kbytes of Flash and 32 Kbytes of static random access
memory (SRAM). On-chip modules include:
• V2 ColdFire core providing 56 Dhrystone 2.1 MIPS @ 60
MHz executing out of on-chip Flash memory using
enhanced multiply accumulate (EMAC) and hardware
divider
• Enhanced Multiply Accumulate Unit (EMAC) and
hardware divide module
• Cryptographic Acceleration Unit (CAU) coprocessor
• Fast Ethernet Controller (FEC)
• On-chip Ethernet Transceiver (EPHY)
• FlexCAN controller area network (CAN) module
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
• Inter-integrated circuit (I
2
C™) bus controller
• Queued serial peripheral interface (QSPI) module
• Eight-channel 10- or 12-bit fast analog-to-digital converter
(ADC)
• Four channel direct memory access (DMA) controller
• Four 32-bit input capture/output compare timers with
DMA support (DTIM)
• Four-channel general-purpose timer (GPT) capable of
input capture/output compare, pulse width modulation
(PWM) and pulse accumulation
• Eight/Four-channel 8/16-bit pulse width modulation timers
(two adjacent 8-bit PWMs can be concatenated to form a
single 16-bit timer)
•
•
•
•
LQFP-80
14mm x 14mm
LQFP-112
20mm_x_20mm
MAPBGA-121
12mm_x_12mm
Two 16-bit periodic interrupt timers (PITs)
Real-time clock (RTC) module
Programmable software watchdog timer
Two interrupt controllers providing every peripheral with a
unique selectable-priority interrupt vector plus seven
external interrupts with fixed levels/priorities
• Clock module with support for crystal or external oscillator
and integrated phase-locked loop (PLL)
• Test access/debug port (JTAG, BDM)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1
MCF52235 Family Configurations . . . . . . . . . . . . . . . . . . . . . .3
1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .22
1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .23
1.8 Fast Ethernet Controller EPHY Signals . . . . . . . . . . . .23
1.9 I
2
C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.10 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.11 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.12 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.13 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .25
1.14 Pulse Width Modulator Signals . . . . . . . . . . . . . . . . . . .25
1.15 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . .25
1.16 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .27
1.17 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .27
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .32
2.4 Phase Lock Loop Electrical Specifications . . . . . . . . . .33
2.5 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .35
2.6 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.7 I
2
C Input/Output Timing Specifications . . . . . . . . . . . . .36
2.8 EPHY Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.9 Analog-to-Digital Converter (ADC) Parameters . . . . . .40
2.10 DMA Timers Timing Specifications . . . . . . . . . . . . . . . .42
2.11 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .42
2.12 QSPI Electrical Specifications. . . . . . . . . . . . . . . . . . . .43
2.13 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . .44
2.14 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . .46
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .47
3.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .47
3.2 112-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . .48
3.3 121 MAPBGA Package. . . . . . . . . . . . . . . . . . . . . . . . .51
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 14.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . .
Figure 15.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . .
Figure 16.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . .
Figure 17.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . .
Figure 19.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . .
44
45
45
45
46
46
List of Tables
Table 1. MCF52235 Family Configurations . . . . . . . . . . . . . . . . . 3
Table 2. Orderable Part Number Summary. . . . . . . . . . . . . . . . 13
Table 3. Pin Functions by Primary and Alternate Purpose . . . . 17
Table 4. Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Mode Selection Signals . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Queued Serial Peripheral Interface (QSPI) Signals. . . 23
Table 9. Fast Ethernet Controller (FEC) Signals . . . . . . . . . . . . 23
Table 10.I
2
C I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11.UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12.DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13.ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14.GPT Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15.PWM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16.Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17.EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . 27
Table 18.Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19.Absolute Maximum Ratings, . . . . . . . . . . . . . . . . . . . 29
Table 20.Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21.ESD Protection Characteristics . . . . . . . . . . . . . . . . . . 31
Table 22.DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 32
Table 23.Active Current Consumption Specifications. . . . . . . . . 33
Table 24.Current Consumption Specifications in Low-Power
Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 25.PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . 33
Table 26.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 27.Reset and Configuration Override Timing . . . . . . . . . . 35
Table 28.I
2
C Input Timing Specifications between I2C_SCL
and I2C_SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 29. I
2
C Output Timing Specifications between I2C_SCL
and I2C_SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 30.EPHY Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 38
Table 31.10BASE-T SQE (Heartbeat) Timing Parameters . . . . 38
Table 32.10BASE-T Jab and Unjab Timing Parameters . . . . . . 39
Table 33.10BASE-T Transceiver Characteristics . . . . . . . . . . . . 40
Table 34.100BASE-TX Transceiver Characteristics . . . . . . . . . . 40
Table 35.ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 36.Timer Module AC Timing Specifications . . . . . . . . . . . 42
Table 37.EzPort Electrical Specifications . . . . . . . . . . . . . . . . . . 42
Table 38.QSPI Modules AC Timing Specifications. . . . . . . . . . . 43
Table 39.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 44
Table 40.Debug AC Timing Specification . . . . . . . . . . . . . . . . . . 46
Table 41.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2
3
4
List of Figures
Figure 1. MCF52235 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. 80-pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . . 14
Figure 3. 112-pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . 15
Figure 4. 121 MAPBGA Pin Assignments . . . . . . . . . . . . . . . . . 16
Figure 5. Suggested Connection Scheme for Power and Ground 28
Figure 6. GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 7. RSTI and Configuration Override Timing . . . . . . . . . . 36
Figure 8. I
2
C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 37
Figure 9. EPHY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10.10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . 39
Figure 11.10BASE-T Jab and Unjab Timing . . . . . . . . . . . . . . . 39
Figure 12.Equivalent Circuit for A/D Loading. . . . . . . . . . . . . . . 42
Figure 13.QSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7
2
Freescale Semiconductor
MCF52235 Family Configurations
1
MCF52235 Family Configurations
Table 1. MCF52235 Family Configurations
Module
52230
•
60
56
128/32
Kbytes
•
•
—
—
•
•
•
2
•
4
•
3
•
•
•
•
•
•
52231
•
60
56
128/32
Kbytes
•
•
—
•
•
•
•
2
•
4
•
3
•
•
•
•
•
•
52232
•
50
46
128/32
Kbytes
•
•
—
—
•
•
•
2
•
4
•
3
•
•
•
•
•
•
52233
•
60
56
256/32
Kbytes
•
•
—
—
•
•
•
2
•
4
•
3
•
•
•
•
•
•
52234
•
60
56
256/32
Kbytes
•
•
—
•
•
•
•
2
•
4
•
3
•
•
•
•
•
•
52235
•
60
56
256/32
Kbytes
•
•
•
•
•
•
•
2
•
4
•
3
•
•
•
•
•
•
52236
•
50
46
256/32
Kbytes
•
•
—
—
•
•
•
2
•
4
•
3
•
•
•
•
•
•
Version 2 ColdFire Core with EMAC
(Enhanced Multiply-Accumulate Unit)
System Clock (MHz)
Performance (Dhrystone 2.1 MIPS)
Flash / Static RAM (SRAM)
Interrupt Controllers (INTC0/INTC1)
Fast Analog-to-Digital Converter (ADC)
Random Number Generator and Crypto
Acceleration Unit (CAU)
FlexCAN 2.0B Module
Fast Ethernet Controller (FEC) with on-chip
interface (EPHY)
Four-channel Direct-Memory Access (DMA)
Software Watchdog Timer (WDT)
Programmable Interrupt Timer
Four-Channel General Purpose Timer
32-bit DMA Timers
QSPI
UART(s)
I
2
C
Eight/Four-channel 8/16-bit PWM Timer
General Purpose I/O Module (GPIO)
Chip Configuration and Reset Controller
Module
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port
1
Package
80 LQFP 80 LQFP 80 LQFP 80 LQFP 112 LQFP 112 LQFP 80 LQFP
112 LQFP 112 LQFP
112 LQFP
121
121
MAPBGA MAPBGA
1
The full debug/trace interface is available only on the 112- and 121-pin packages. A reduced debug interface is bonded on the
80-pin package.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
3
MCF52235 Family Configurations
1.1
Block Diagram
The MCF52235 (or its variants) comes in 80- and 112-pin low-profile quad flat pack packages (LQFP) and a 121 MAPBGA,
and operates in single-chip mode only.
Figure 1
shows a top-level block diagram of the MCF52235.
EPHY_TX EzPD
EPHY_RX EzPQ
EzPort
EzPCK
EzPCS
Interrupt
Controller 1
Interrupt
Controller 2
PADI – Pin Muxing
GPTn
QSPI_DIN,
QSPI_DOUT
QSPI_CLK,
QSPI_CSn
SDA
SCL
UTXDn
URXDn
URTSn
UCTSn
DTINn/DTOUTn
CANRX
CANTX
PWMn
EPHY
Arbiter
Fast
Ethernet
Controller
(FEC)
4 CH DMA
To/From PADI
UART
0
UART
1
UART
2
I
2
C
QSPI
DTIM
0
DTIM
1
DTIM
2
DTIM
3
RTC
JTAG_EN
MUX
V2 ColdFire CPU
JTAG
TAP
IFP
OEP
CAU
EMAC
PMM
AN[7:0]
ADC
32 Kbytes
SRAM
(4K×16)×4
256 Kbytes
Flash
(32K×16)×4
PORTS
(GPIO)
CIM
RSTIN
RSTOUT
V
RH
V
RL
Edge
Port 1
Edge
Port 2
PLL
CLKGEN
FlexCAN
PIT1
PWM
EXTAL XTAL CLKOUT
RNGA
PIT0
GPT
To/From Interrupt Controller
Figure 1. MCF52235 Block Diagram
1.2
Features
This document contains information on a new product under development. Freescale reserves the right to change or discontinue
this product without notice. Specifications and information herein are subject to change without notice.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7
4
Freescale Semiconductor
MCF52235 Family Configurations
1.2.1
•
Feature Overview
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 60 MHz processor core frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions
for improved bit processing (ISA_A+)
— Enhanced Multiply-Accumulate (EMAC) unit with 32-bit accumulator to support 16
×
16
→
32 or 32
×
32
→
32
operations
— Cryptography Acceleration Unit (CAU)
– Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions
– FIPS-140 compliant random number generator
— Support for DES, 3DES, AES, MD5, and SHA-1 algorithms
— Illegal instruction decode that allows for 68K emulation support
System debug support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can be configured into
a 1- or 2-level trigger
On-chip memories
— Up to 32 Kbytes of dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power
supply support
— Up to 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
Fast Ethernet Controller (FEC)
— 10/100 BaseT/TX capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
The MCF52235 family includes the following features:
•
•
•
•
•
On-chip Ethernet Transceiver (EPHY)
— Digital adaptive equalization
— Supports auto-negotiation
— Baseline wander correction
— Full-/Half-duplex support in all modes
— Loopback modes
— Supports MDIO preamble suppression
— Jumbo packet
•
FlexCAN 2.0B module
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
5
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