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MT58L256V32PF-5

Description
Cache SRAM, 256KX32, 3.1ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
Categorystorage    storage   
File Size656KB,32 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

MT58L256V32PF-5 Overview

Cache SRAM, 256KX32, 3.1ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165

MT58L256V32PF-5 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeBGA
package instructionTBGA,
Contacts165
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time3.1 ns
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length15 mm
memory density8388608 bit
Memory IC TypeCACHE SRAM
memory width32
Humidity sensitivity level3
Number of functions1
Number of terminals165
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX32
Package body materialPLASTIC/EPOXY
encapsulated codeTBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)220
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width13 mm
Base Number Matches1
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
8Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
DD
)
• Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium
®
BSRAM-compatible)
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion
and address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-pin TQFP package
• 165-pin FBGA package
• 119-pin BGA package
• Low capacitive bus loading
• x18, x32, and x36 versions available
MT58L512L18P, MT58L256L32P, MT58L256L36P;
MT58L512V18P, MT58L256V32P, MT58L256V36P
3.3V V
DD
, 3.3V or 2.5V I/O, Pipelined, Single-Cycle
Deselect
100-Pin TQFP
1
165-Pin FBGA
(Preliminary Package Data)
OPTIONS
• Timing (Access/Cycle/MHz)
3.1ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
512K x 18
256K x 32
256K x 36
2.5V I/O
512K x 18
256K x 32
256K x 36
• Packages
100-pin TQFP (2-chip enable)
100-pin TQFP (3-chip enable)
165-pin, 13mm x 15mm FBGA
119-pin, 14mm x 22mm BGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
MARKING
-5
-6
-7.5
-10
MT58L512L18P
MT58L256L32P
MT58L256L36P
MT58L512V18P
MT58L256V32P
MT58L256V36P
T
S
F*
B
None
IT
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-standard MS-028 BHA (PBGA).
119-Pin BGA
2
Part Number Example:
MT58L512L18PT-6
* A Part Marking Guide for the FBGA devices can be found on Micron’s
web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_2.p65 – Rev. 6/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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