2SK1764
Silicon N Channel MOS FET
REJ03G0970-0200
(Previous: ADE-208-1317)
Rev.2.00
Sep 07, 2005
Application
•
Low frequency amplifier
•
High speed switching
Features
•
•
•
•
Low on-resistance
High speed switching
4 V Gate drive device can be driven from 5 V source
Suitable for switching regulator, DC-DC converter
Outline
RENESAS Package code: PLZZ0004CA-A
(Package name: UPAK
R
)
3
2 1
G
4
D
1. Gate
2. Drain
3. Source
4. Drain
S
Note:
Marking is "KY".
*UPAK is a trademark of Renesas Technology Corp.
Rev.2.00 Sep 07, 2005 page 1 of 6
2SK1764
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body to drain diode reverse drain current
Channel power dissipation
Channel temperature
Symbol
V
DSS
V
GSS
I
D
I
D(pulse)
I
DR
*1
Ratings
60
±20
2
4
2
1
150
–55 to +150
Unit
V
V
A
A
A
W
°
C
Pch
*2
Tch
Storage temperature
Tstg
Notes: 1. PW
≤
100
µs,
duty cycle
≤
10 %
2. Value on the alumina ceramic board (12.5 x 20 x 0.7 mm)
°
C
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate to source breakdown voltage
Gate to source cutoff voltage
Drain to source cutoff current
Gate to source cutoff current
Static drain to source on state
resistance
Static drain to source on state
resistance
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn on time
Turn off time
Note:
3. Pulse Test
Symbol
V
(BR)DSS
V
(BR)GSS
V
GS(off)
I
DSS
I
GSS
R
DS(on)1
R
DS(on)2
|y
fs
|
Ciss
Coss
Crss
t
on
t
off
Min
60
±20
1
—
—
—
—
0.9
—
—
—
—
—
Typ
—
—
—
—
—
0.3
0.4
1.7
140
75
20
18
80
Max
—
—
2
10
±5
0.45
0.60
—
—
—
—
—
—
Unit
V
V
V
µA
µA
Ω
Ω
S
pF
pF
pF
ns
ns
Test Conditions
I
D
= 10 mA, V
GS
= 0
I
G
=
±100 µA,
V
DS
= 0
V
DS
= 10 V, I
D
= 1 mA
V
DS
= 50 V, V
GS
= 0
V
GS
=
±15
V, V
DS
= 0
V
GS
= 10 V, I
D
= 1 A*
V
GS
= 4 V, I
D
= 1 A*
3
3
V
DS
= 10 V, I
D
= 1 A*
V
DS
= 10 V, V
GS
= 0,
f = 1 MHz
3
V
DS
= 10 V, I
D
= 1 A* ,
R
L
= 30
Ω
3
Rev.2.00 Sep 07, 2005 page 2 of 6
2SK1764
Main Characteristics
Maximum Channel Power
Dissipation Curve
1.6
10
Channel Power Dissipation Pch** (W)
(** on the almina ceramic board)
Safe Operation Area
I
D
(A)
3
PW
1
m
1.2
=
10
s
1.0
0.3
0.1
0.03
in
n)
(o
ti
is
DS
ra a R
pe re y
O is a d b
th ite
lim
on
D
s
m
Drain Current
C
sh
(1
0.8
op
er
)
ot
at
io
n
0.4
Ta = 25°C
0.3
1.0
3
10
30
100
0
50
100
150
200
0.01
0.1
Ambient Temperature
Ta (°C)
Drain to Source Voltage
V
DS
(V)
Typical Output Characteristics
5
Typical Transfer Characteristics
5
10 V
Drain Current I
D
(A)
Drain Current I
D
(A)
4
4.5 V
Pulse Test
5V
7V
4V
4
V
DS
= 10 V
Pulse Test
3
3.5 V
3
2
3V
2
1
V
GS
= 2.5 V
1
75
°
C
–25
°
C
T
C
= 25°C
2
3
4
5
0
2
4
6
8
10
0
1
Drain to Source Voltage V
DS
(V)
Gate to Source Voltage V
GS
(V)
Static Drain to Source on State Resistance
R
DS (on)
(Ω)
Drain to Source Saturation Voltage
vs. Gate to Source Voltage
Drain to Source Saturation Voltage
V
DS (on)
(V)
1.0
0.8
Static Drain to Source On State
Resistance vs. Drain Current
5
Pulse Test
Pulse Test
2
V
GS
= 4 V
2A
1.0
0.5
0.2
0.1
0.05
0.05
0.6
0.4
10 V
1A
I
D
= 0.5 A
0.2
0
2
4
6
8
10
0.1
0.2
0.5
1.0
2
5
Gate to Source Voltage V
GS
(V)
Drain Current I
D
(A)
Rev.2.00 Sep 07, 2005 page 3 of 6
2SK1764
Static Drain to Source on State
Resistance vs. Temperature
Pulse Test
I
D
= 2 A
1A
0.5 A
V
GS
= 4 V
Forward Transfer Admittance
y
fs
(S)
Static Drain to Source on State Resistance
R
DS (on)
(Ω)
Forward Transfer Admittance
vs. Drain Current
5
2
1.0
0.5
V
DS
= 10 V
–25
°
C
Pulse Test T = 25°C
C
1.0
0.8
0.6
75
°
C
0.4
V
GS
= 10 V
2 A 0.5 A
1A
0.2
0.1
0.05
0.05
0.2
0
–40
0
40
80
120
160
0.1
0.2
0.5
1.0
2
5
Case Temperature T
C
(°C)
Drain Current I
D
(A)
Body to Drain Diode Reverse
Recovery Time
1000
1000
di/dt = 50 A/µs, Ta = 25°C
V
GS
= 0
Pulse Test
Capacitance C (pF)
Typical Capacitance vs.
Drain to Source Voltage
V
GS
= 0
f = 1 MHz
Ciss
100
30
Crss
10
3
1
Coss
Reverse Recovery Time trr (ns)
500
300
200
100
50
20
10
0.05
0.1
0.2
0.5
1.0
2
5
0
10
20
30
40
50
Reverse Drain Current I
DR
(A)
Drain to Source Voltage V
DS
(V)
Dynamic Input Characteristics
Drain to Source Voltage V
DS
(V)
100
80
V
DD
= 50 V
25 V
10 V
60
V
DS
V
DD
= 50 V
V
GS
12
20
100
Switching Characteristics
Gate to Source Voltage V
GS
(V)
td (off)
50
Switching Time t (ns)
16
20
10
5
tf
V
GS
= 10 V V
DD
= 30 V
PW = 2
µs,
duty < 1 %
•
•
tr
40
20
8
4
td (on)
2
1
0.05
25 V
10 V
0
2
4
6
I
D
= 1.5 A
8
0
10
0.1
0.2
0.5
1.0
2
5
Gate Charge Qg (nc)
Drain Current I
D
(A)
Rev.2.00 Sep 07, 2005 page 4 of 6
2SK1764
Reverse Drain Current vs.
Source to Drain Voltage
2.0
Reverse Drain Current I
DR
(A)
Pulse Test
1.6
10 V
15 V
5V
0.8
0.4
V
GS
= 0, –5 V
1.2
0
0.4
0.8
1.2
1.6
2.0
Source to Drain Voltage V
SD
(V)
Rev.2.00 Sep 07, 2005 page 5 of 6
FPGA/CPLD
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