HD74LV1GT08AVSE datasheet, PDF

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HD74LV1GT08AVSE: Description2.input AND Gate / CMOS Logic Level Shifter; Categorylogic logic; File Size97KB，7 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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HD74LV1GT08AVSE Overview

2.input AND Gate / CMOS Logic Level Shifter

HD74LV1GT08AVSE Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
Parts packaging code	SON
package instruction	VSOF, FL5/6,.047,20
Contacts	5
Reach Compliance Code	compli
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-F5
JESD-609 code	e0
length	1.6 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	AND GATE
MaximumI(ol)	0.006 A
Humidity sensitivity level	1
Number of functions	1
Number of entries	2
Number of terminals	5
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	VSOF
Encapsulate equivalent code	FL5/6,.047,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Prop。Delay @ Nom-Su	14 ns
propagation delay (tpd)	14 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	0.6 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	FLAT
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	1.2 mm
Base Number Matches	1

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HD74LV1GT08A

2–input AND Gate / CMOS Logic Level Shifter

REJ03D0118-0900

Rev.9.00

Mar 21, 2008

Description

The HD74LV1GT08A is high-speed CMOS two input AND gate using silicon gate CMOS process. With CMOS low

power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of three stages construction

with buffer provides wide noise margin and stable output. The input protection circuitry on this device allows over

voltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0

V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply.

Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the

low power consumption extends the battery life.

Features

•

The basic gate function is lined up as Renesas uni logic series.

•

Supplied on emboss taping for high-speed automatic mounting.

•

TTL compatible input level.

Supply voltage range : 3.0 to 5.5 V

Operating temperature range : –40 to +85°C

•

Logic-level translate function

3.0 V CMOS logic

→

5.0 V CMOS logic (@V

= 5.0 V)

1.8 V or 2.5 V CMOS logic

→

3.3 V CMOS logic (@V

= 3.3 V)

•

All inputs V

(Max.) = 5.5 V (@V

= 0 V to 5.5 V)

All outputs V

(Max.) = 5.5 V (@V

= 0 V)

•

Output current ±6 mA (@V

= 3.0 V to 3.6 V), ±12 mA (@V

= 4.5 V to 5.5 V)

•

All the logical input has hysteresis voltage for the slow transition.

•

Ordering Information

Part Name

HD74LV1GT08ACME

HD74LV1GT08AVSE

Note:

Package Type

CMPAK–5 pin

VSON–5 pin

Package Code

(Previous Code)

PTSP0005ZC-A

(CMPAK-5V)

PUSN0005KA-A

(TNP-5DV)

Package

Abbreviation

Taping Abbreviation

(Quantity)

E (3000 pcs/reel)

Please consult the sales office for the above package availability.

REJ03D0118-0900 Rev.9.00, Mar 21, 2008

Page 1 of 6

HD74LV1GT08AVSE Related Products

	HD74LV1GT08AVSE	HD74LV1GT08A	HD74LV1GT08ACME	HD74LV1GT08A_08
Description	2.input AND Gate / CMOS Logic Level Shifter	2.input AND Gate / CMOS Logic Level Shifter	2.input AND Gate / CMOS Logic Level Shifter	2.input AND Gate / CMOS Logic Level Shifter
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	-
Parts packaging code	SON	SOIC	SOIC	-
package instruction	VSOF, FL5/6,.047,20	TSSOP,	TSSOP, TSSOP5/6,.08	-
Contacts	5	5	5	-
Reach Compliance Code	compli	compli	compli	-
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	-
JESD-30 code	R-PDSO-F5	R-PDSO-G5	R-PDSO-G5	-
JESD-609 code	e0	e6	e0	-
length	1.6 mm	2 mm	2 mm	-
Logic integrated circuit type	AND GATE	AND GATE	AND GATE	-
Number of functions	1	1	1	-
Number of entries	2	2	2	-
Number of terminals	5	5	5	-
Maximum operating temperature	85 °C	85 °C	85 °C	-
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	VSOF	TSSOP	TSSOP	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-
propagation delay (tpd)	14 ns	9 ns	14 ns	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	0.6 mm	1.1 mm	1.1 mm	-
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	-
Minimum supply voltage (Vsup)	3 V	4.5 V	3 V	-
Nominal supply voltage (Vsup)	3.3 V	5 V	3.3 V	-
surface mount	YES	YES	YES	-
technology	CMOS	CMOS	CMOS	-
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	-
Terminal form	FLAT	GULL WING	GULL WING	-
Terminal pitch	0.5 mm	0.65 mm	0.65 mm	-
Terminal location	DUAL	DUAL	DUAL	-
width	1.2 mm	1.25 mm	1.25 mm	-

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