HN58X25128IAG
HN58X25256IAG
Serial Peripheral Interface
128k EEPROM (16-kword
×
8-bit)
256k EEPROM (32-kword
×
8-bit)
Electrically Erasable and Programmable Read Only Memory
REJ03C0307-0100
Rev.1.00
Nov.30.2006
Description
HN58X25xxx Series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and
Programmable ROM). It realizes high speed, low power consumption and a high level of reliability by employing
advanced MONOS memory technology and CMOS process and low voltage circuitry technology. It also has a 64-byte
page programming function to make it’s write operation faster.
Features
•
Single supply: 1.8 V to 5.5 V
•
Serial Peripheral Interface compatible (SPI bus)
SPI mode 0 (0,0), 3 (1,1)
•
Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V)
•
Power dissipation:
Standby: 3
µA
(max)
Active (Read): 4 mA (max)
Active (Write): 4 mA (max)
•
Automatic page write: 64-byte/page
•
Write cycle time: 5 ms (2.5 V min), 8 ms (1.8 V min)
•
Endurance: 10
6
Erase/Write Cycles
•
Data retention: 10 Years
•
Small size packages: SOP-8pin and TSSOP-14pin
•
Shipping tape and reel
TSSOP-14pin : 2,000 IC/reel
SOP-8pin
: 2,500 IC/reel
•
Temperature range:
−40
to
+85°C
•
Lead free product.
Rev.1.00, Nov.30.2006, page 1 of 20
HN58X25128IAG/HN58X25256IAG
Ordering Information
Type No.
Internal organization
Operating voltage
1.8 V to 5.5 V
Frequency
5 MHz
(2.5 V to 5.5 V)
3 MHz
(1.8 V to 5.5 V)
1.8 V to 5.5 V
5 MHz
(2.5 V to 5.5 V)
3 MHz
(1.8 V to 5.5 V)
HN58X25128FPIAG 128-kbit (16834
×
8-bit)
HN58X25256FPIAG 256-kbit (32768
×
8-bit)
HN58X25128TIAG
HN58X25256TIAG
128-kbit (16834
×
8-bit)
256-kbit (32768
×
8-bit)
Package
150mil 8-pin plastic SOP
PRSP0008DF-B
(FP-8DBV)
Lead free
14-pin plastic TSSOP
PTSP0014JA-C
(TTP-14DBV)
Lead free
Pin Arrangement
8-pin SOP
S
Q
W
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
C
D
S
Q
NC
NC
NC
1
2
3
4
5
6
7
14-pin TSSOP
14
13
12
11
10
9
8
V
CC
HOLD
NC
NC
NC
(Top view)
W
V
SS
C
D
(Top view)
Pin Description
Pin name
C
D
Q
S
W
HOLD
V
CC
V
SS
Function
Serial clock
Serial data input
Serial data output
Chip select
Write protect
Hold
Supply voltage
Ground
Rev.1.00, Nov.30.2006, page 2 of 20
HN58X25128IAG/HN58X25256IAG
Block Diagram
High voltage generator
V
CC
V
SS
Address generator
X
decoder
W
C
HOLD
D
Q
Control logic
S
Memory array
Y
decoder
Y-select & Sense amp.
Serial-parallel converter
Absolute Maximum Ratings
Parameter
Supply voltage relative to V
SS
Input voltage relative to V
SS
Operating temperature range*
1
Symbol
V
CC
V
IN
Topr
Value
−0.6
to + 7.0
−0.5*
2
to +7.0*
3
−40
to +85
−65
to +125
Unit
V
V
°C
°C
Storage temperature range
Tstg
Notes: 1. Including electrical characteristics and data retention.
2. V
IN
(min):
−3.0
V for pulse width
≤
50 ns.
3. Should not exceed V
CC
+
1.0 V.
DC Operating Conditions
Parameter
Supply voltage
Input voltage
Operating temperature range
Symbol
V
CC
V
SS
V
IH
V
IL
Topr
Min
1.8
0
V
CC
×
0.7
−0.3*
1
−40
Typ
0
Max
5.5
0
V
CC
+
0.5*
2
V
CC
×
0.3
+85
Unit
V
V
V
V
°C
Notes: 1. V
IN
(min):
−1.0
V for pulse width
≤
50 ns.
2. V
IN
(max): V
CC
+ 1.0 V for pulse width
≤
50 ns.
Rev.1.00, Nov.30.2006, page 3 of 20
HN58X25128IAG/HN58X25256IAG
DC Characteristics
Parameter
Input leakage current
Output leakage current
V
CC
current
Standby
Active
Symbol
I
LI
I
LO
I
SB
I
CC1
Min
Max
2
2
3
2.5
Unit
µA
µA
µA
mA
Test conditions
V
CC
= 5.5 V, V
IN
= 0 to 5.5 V
(S, D, C,
HOLD, W)
V
CC
= 5.5 V, V
OUT
= 0 to 5.5 V
(Q)
V
IN
= V
SS
or V
CC
,
V
CC
= 5.5 V
V
CC
= 3.6 V, Read at 5 MHz
V
IN
= V
CC
×
0.1/V
CC
×
0.9
Q = OPEN
V
CC
= 5.5 V, Read at 5 MHz
V
IN
= V
CC
×
0.1/V
CC
×
0.9
Q = OPEN
V
CC
= 3.6 V, Write at 5 MHz
V
IN
= V
CC
×
0.1/V
CC
×
0.9
V
CC
= 5.5 V, Write at 5 MHz
V
IN
= V
CC
×
0.1/V
CC
×
0.9
V
CC
= 5.5 V, I
OL
= 2 mA
V
CC
= 2.5 V, I
OL
= 1.5 mA
V
CC
= 5.5 V, I
OL
=
−2
mA
V
CC
= 2.5 V, I
OL
=
−0.4
mA
4
mA
I
CC2
2.5
4
0.4
0.4
mA
mA
V
V
V
V
Output voltage
V
OL1
V
OL2
V
OH1
V
OH2
V
CC
×
0.8
V
CC
×
0.8
Rev.1.00, Nov.30.2006, page 4 of 20
HN58X25128IAG/HN58X25256IAG
AC Characteristics
Test Conditions
•
Input pules levels:
V
IL
= V
CC
×
0.2
V
IH
= V
CC
×
0.8
•
Input rise and fall time:
≤
10 ns
•
Input and output timing reference levels: V
CC
×
0.3, V
CC
×
0.7
•
Output reference levels: V
CC
×
0.5
•
Output load: 100 pF
Parameter
Clock frequency
S
active setup time
S
not active setup time
S
deselect time
S
active hold time
S
not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after
HOLD
not active
Clock low hold time after
HOLD
active
Clock high setup time before
HOLD
active
Clock high setup time before
HOLD
not
active
Symbol
f
C
t
SLCH
t
SHCH
t
SHSL
t
CHSH
t
CHSL
t
CH
t
CL
t
CLCH
t
CHCL
t
DVCH
t
CHDX
t
HHCH
t
HLCH
t
CHHL
t
CHHH
Alt
f
SCK
t
CSS1
t
CSS2
t
CS
t
CSH
—
t
CLH
t
CLL
t
RC
t
FC
t
DSU
t
DH
Min
90
90
90
90
90
90
90
20
30
70
40
60
60
(Ta =
−40
to
+85°C,
V
CC
= 2.5 V to 5.5 V)
Max
5
—
1
1
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
cycles
Notes
1
1
2
2
Output disable time
t
SHQZ
t
DIS
100
Clock low to output valid
t
CLQV
t
V
70
Output hold time
t
CLQX
t
HO
0
Output rise time
t
QLQH
t
RO
50
Output fall time
t
QHQL
t
FO
50
HOLD
high to output low-Z
t
HHQX
t
LZ
50
HOLD
low to output low-Z
t
HLQZ
t
HZ
100
Write time
t
W
t
WC
5
6
Erase / Write Endurance
10
Notes: 1. t
CH
+
t
CL
≥
1/f
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Value guaranteed by characterization, not 100% tested in products (Ta = 25°C).
2
2
2
2
2
3
Rev.1.00, Nov.30.2006, page 5 of 20
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