M32C/80 Group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
REJ03B0038-0110
Rev.1.10
Nov. 01, 2005
1. Overview
The M32C/80 Group microcomputer is a single-chip control unit that utilizes high-performance silicon gate
CMOS technology with the M32C/80 series CPU core. The M32C/80 Group is available in 100-pin plastic
molded LQFP/QFP package.
With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabili-
ties to process complex instructions by less bytes and execute instructions at higher speed.
It incorporates a multiplier and DMAC adequate for office automation, communication devices and industrial
equipments and other high-speed processing applications.
The M32C/80 Group is ROMless device.
Use the M32C/80 Group in microprocessor mode after reset.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
Rev. 1.10 Nov. 01, 2005 page 1
REJ03B0038-0110
of 56
M32C/80 Group
1. Overview
1.2 Performance Overview
Table 1.1 lists performance overview of the M32C/80 Group.
Table 1.1 M32C/80 Group Performance
CPU
Item
Basic Instructions
Minimum Instruction Execution Time
Performance
108 instructions
31.3 ns ( f(BCLK)=32 MHz, V
CC1
=4.2 to 5.5 V )
41.7 ns ( f(BCLK)=24 MHz, V
CC1
=3.0 to 5.5 V )
Single-chip mode, Memory expansion mode, Microprocessor mode
16 Mbytes
See Table 1.2
47 I/O pins (when using 16-bit bus) and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
2 channels
5 channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus
(1)
, I
2
C Bus
(2)
10-bit A/D converter: 1 circuit, 10 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt sources
Immediate transfer, operation and chain transfer function
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
34 internal sources and 8 external sources, 5 software sources
Interrupt priority level: 7
4 circuits
Main Clock oscillation circuit (*), Sub clock oscillation circuit (*),
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor
Main clock oscillation stop detect circuit
V
CC1
=4.2 to 5.5 V, V
CC2
=3.0 to V
CC1
(f(BCLK)=32 MHz)
V
CC1
=3.0 to 5.5 V, V
CC2
=3.0 to V
CC1
(f(BCLK)=24 MHz)
22 mA (V
CC1
=V
CC2
=5 V, f(BCLK)=32 MHz)
17 mA (V
CC1
=V
CC2
=3.3 V, f(BCLK)=24 MHz)
10
µA
(V
CC1
=V
CC2
=3.3 V, f(BCLK)=32 kHz, in wait mode)
–20 to 85
o
C, –40 to 85
o
C(optional)
100-pin plastic molded LQFP/QFP
Operating Mode
Memory Space
Memory Capacity
Peripheral I/O Port
function Multifunction Timer
Intelligent I/O Communication Function
Serial I/O
A/D Converter
D/A Converter
DMAC
DMAC II
CRC Calculation Circuit
X/Y Converter
Watchdog Timer
Interrupt
Clock Generation Circuit
Oscillation Stop Detect Function
Electrical Supply Voltage
Charact-
eristics Power Consumption
Operating AmbientTemperature
Package
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
All options are on a request basis.
Rev. 1.10 Nov. 01, 2005
REJ03B0038-0110
page 2
of 56
M32C/80 Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows a block diagram of the M32C/80 Group microcomputer.
8
(1)
8
(2)
8
(1)
8
(1)
8
(1)
8
(1)
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
<
V
CC2
>
Port P6
Peripheral Functions
A/D Converter
1 circuit
Standard: 8 inputs
Maximum: 10 inputs
Timer (16 bits)
Timer A: 5 channels
Timer B: 6 channels
UART/
Clock Synchronous Serial I/O
5 channels
Clock Generating Circuit
X
IN
- X
OUT
X
CIN
- X
COUT
On-chip Oscillator
PLL Frequency Synthesizer
DMAC
DMACII
8
Port P7
Port P8
8
Three-phase Motor Control Circuit
X/Y converter
16 bits X 16 bits
CRC Calcilation Circuit (CCITT)
X
16
+X
12
+X
5
+1
7
<
V
CC1
>
Watchdog Timer (15 bits)
R0H
R1H
D/A Converter
8 bits X 2 channels
A0
Intelligent I/O
Communication Function
2 channels
A1
FB
SB
R2
R3
M32C/80 series CPU core
R0L
R1L
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
Memory
P8
5
RAM
Port P9
Port P10
8
Multiplier
8
NOTES:
1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode.
2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor mode
and all external data buses are selected as 8-bit buses.
Figure 1.1 M32C/80 Group Block Diagram
Rev. 1.10 Nov. 01, 2005 page 3
REJ03B0038-0110
of 56
M32C/80 Group
1. Overview
1.4 Product Information
Table 1.2 lists the product information. Figure 1.2 shows the product numbering system.
Table 1.2 M32C/80 Group
Type Number
M30800SAGP
M30800SAFP
M30800SAGP-BL
M30800SAFP-BL
Package Type
PLQP0100KB-A (100P6Q-A)
ROMless
PRQP0100JB-A (100P6S-A)
PLQP0100KB-A (100P6Q-A)
PRQP0100JB-A (100P6S-A)
ROM
Capacity
As of November, 2005
RAM
Capacity
Remarks
−
8K
ROMless with
on-chip boot loader
M30800 S A GP -BL
On-chip boot loader
Package type:
FP = Package PRQP0100JB-A (100P6S-A)
GP = Package PLQP0100KB-A (100P6Q-A)
Memory type:
S = ROMless version
RAM capacity, pin count, etc
M32C/80 Group
M16C Family
Figure 1.2 Product Numbering System
Rev. 1.10 Nov. 01, 2005
REJ03B0038-0110
page 4
of 56
M32C/80 Group
STxD4 / SCL4 /
RxD4 / AD
TRG
/ P9
7
KI
0
/ AN
4
/ P10
4
KI
1
/ AN
5
/ P10
5
KI
2
/ AN
6
/ P10
6
KI
3
/ AN
7
/ P10
7
AN
1
/ P10
1
D
0
/ P0
0
D
1
/ P0
1
D
2
/ P0
2
D
3
/ P0
3
D
4
/ P0
4
D
5
/ P0
5
D
6
/ P0
6
D
7
/ P0
7
AN
2
/ P10
2
AN
3
/ P10
3
AN
0
/ P10
0
AVss
88
81
97
96
95
94
93
92
91
90
89
87
86
85
84
83
82
V
REF
98
AVcc
99
1.5 Pin Assignment
NOTE:
100
SRxD4 / SDA4 / TxD4 / ANEX1 / P9
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
74
75
76
77
78
P1
2
/ D
10
P1
3
/ D
11
P1
4
/ D
12
P1
5
/ D
13
/ INT3
P1
6
/ D
14
/ INT4
P1
7
/ D
15
/ INT5
P2
0
/ A
0
( / D
0
)
P2
1
/ A
1
( / D
1
)
P2
2
/ A
2
( / D
2
)
P2
3
/ A
3
( / D
3
)
P2
4
/ A
4
( / D
4
)
P2
5
/ A
5
( / D
5
)
P2
6
/ A
6
( / D
6
)
P2
7
/ A
7
( / D
7
)
Vss
P3
0
/ A
8
( / D
8
)
Vcc2
P3
1
/ A
9
( / D
9
)
P3
2
/ A
10
( / D
10
)
P3
3
/ A
11
( / D
11
)
P3
4
/ A
12
( / D
12
)
P3
5
/ A
13
( / D
13
)
P3
6
/ A
14
( / D
14
)
P3
7
/ A
15
( / D
15
)
P4
0
/ A
16
P4
1
/ A
17
P4
2
/ A
18
P4
3
/ A
19
79
P1
1
/ D
9
80
CLK4 / ANEX0 / P9
5
SS4 / RTS4 / CTS4 / TB4
IN
/ DA1 / P9
4
SS3 / RTS3 / CTS3 / TB3
IN
/ DA0 / P9
3
SRxD3 / SDA3 / TxD3 / TB2
IN
/ P9
2
STxD3 / SCL3 / RxD3 / TB1
IN
/ P9
1
CLK3 / TB0
IN
/ P9
0
BYTE
CNVss
X
CIN
/ P8
7
X
COUT
/ P8
6
RESET
X
OUT
Vss
X
IN
Vcc1
NMI / P8
5
INT2 / P8
4
INT1 / P8
3
INT0 / P8
2
U / TA4
IN
/ P8
1
ISRxD0 / U / TA4
OUT
/ P8
0
ISCLK0 / TA3
IN
/ P7
7
ISTxD0 / TA3
OUT
/ P7
6
ISRxD1 / W / TA2
IN
/ P7
5
ISCLK1 / W / TA2
OUT
/ P7
4
ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1
IN
/ P7
3
CLK2 / V / TA1
OUT
/ P7
2
STxD2 / SCL2 / RxD2 / TA0
IN
/ TB5
IN
/ P7
1
SRxD2 / SDA2 / TxD2 / TA0
OUT
/ P7
0
P1
0
/ D
8
Figure 1.3 Pin Assignment
Rev. 1.10 Nov. 01, 2005 page 5
REJ03B0038-0110
Figures 1.3 and 1.4 show pin assignments (top view).
1. P7
0
and P7
1
are ports for the N-channel open drain output.
of 56
<
V
CC2
>
M32C/80 GROUP
<
V
CC1
>
33
P6
5
/ CLK1
44
31
32
34
P6
4
/ CTS1 / RTS1 / SS1
35
36
37
P6
1
/ CLK0
38
P6
0
/ CTS0 / RTS0 / SS0
39
P5
7
/ RDY
40
P5
6
/ ALE
41
P5
5
/ HOLD
42
P5
4
/ HLDA / ALE
43
45
P5
2
/ RD
P5
1
/ WRH / BHE
46
P5
0
/ WRL / WR
47
P4
7
/ CS0 / A
23
48
P4
6
/ CS1 / A
22
49
P4
5
/ CS2 / A
21
50
P4
4
/ CS3 / A
20
PRQP0100JB-A
(100P6S-A)
P6
6
/ RxD1 / SCL1 / STxD1
P6
2
/ RxD0 / SCL0 / STxD0
P5
3
/ CLK
OUT
/ BCLK / ALE
P6
7
/ TxD1 / SDA1 / SRxD1
P6
3
/ TxD0 / SDA0 / SRxD0
1. Overview
京公网安备 11010802033920号
EEWORLD
