M306H7MG-XXXFP/MC-XXXFP/FGFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
REJ03B0152-0210
Rev.2.10
Oct 25, 2006
1.
DESCRIPTION
The M306H7MG/MC-XXXFP and M306H7FGFP are single-chip microcomputers using the high-
performance silicon gate CMOS process using M16C/62 Series CPU core and is packaged in a 100-pin
plastic molded QFP. This single-chip microcomputer operates using sophisticated instructions featuring a
high level of instruction efficiency. With 1M bytes of address space, this is capable of executing instructions
at high speed. This also features a built-in data slicer, making this correspondence to Global broadcasting
service.
1.1
Features
Mask version : 256 K/128 K bytes
Flash memory version : 256 K bytes
RAM
Mask version : 8 K/5 K bytes
Flash memory version : 8 K bytes
• Shortest instruction execution time ..62.5 ns (f(X
IN
)=16 MHz)
• Supply voltage ..................................V
CC1
=3.00 V to V
CC2
, V
CC2
=4.5 V to 5.5 V(at f(X
IN
)=16 MHz)
V
CC1
=2.00 V to V
CC2
, V
CC2
=2.00 V to 5.5 V(at f(X
CIN
)=32 kHz)
*V
CC2
=2.0 V to 2.9 V: Operates only in the low power dissipation
mode
• Interrupts ..........................................25 internal and 8 external interrupt sources, 4 software
interrupt sources; 7 levels
• Multifunction 16-bit timer ..................5 output timers + 6 input timers
• Serial I/O ..........................................6 channels
UART/clock synchronous: 3
Clock synchronous: 2
Multi-master I
2
C: 1
• DMAC...............................................2 channels (trigger: 24 sources)
• A/D converter ...................................8 bits X 8 channels (Expandable up to 10 channels)
• CRC calculation circuit ....................1 circuit
• Watchdog timer ................................1 line
• Programmable I/O ............................79 lines (P6 to P7, P8
0
to P8
4
: Can be used as 3.3 V interface)
• Input port ..........................................1 port (P8
5
shared with NMI pin)
• Clock generating circuit ....................2 built-in circuits
(built-in feedback resistor, external crystal oscillator is required)
• Data slicer ........................................For PDC, VPS, WSS, EPG-J, CC, CC2X, ID-1
• Memory capacity ..............................ROM
1.2
Applications
DVD recorder, HDD recorder
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 1 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
------Table of Contents------
1. DESCRIPTION.............................................................1
1.1 Features ..........................................................1
1.2 Applications.....................................................1
Table of Contents ......................................................2
1.3 Pin Configuration.............................................3
1.4 Performance Outline .......................................4
1.5 Block Diagram.................................................6
1.6 Memory .........................................................10
2. CENTRAL PROCESSING UNIT (CPU)..................... 11
2.1 Data Registers (R0, R1, R2 and R3)............. 11
2.2 Address Registers (A0 and A1)..................... 11
2.3 Frame Base Register (FB) ............................12
2.4 Interrupt Table Register (INTB) .....................12
2.5 Program Counter (PC) ..................................12
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ..12
2.7 Static Base Register (SB)..............................12
2.8 Flag Register (FLG) ......................................12
3. RESET ......................................................................13
3.1 Hardware Reset ............................................13
3.2 Software Reset..............................................14
3.3 Watchdog Timer Reset..................................14
3.4 SFR ...............................................................17
4. CLOCK GENERATION CIRCUIT ..............................25
4.1 Oscillator Circuit ............................................30
4.2 CPU Clock and Peripheral Function Clock ...33
4.3 Clock Output Function...................................33
4.4 Power Control ...............................................35
4.5 System Clock Protective Function ................41
5. PROTECTION............................................................42
6. INTERRUPTS ............................................................43
6.1 Type of Interrupts ..........................................43
6.2 Software Interrupts ........................................44
6.3 Hardware Interrupts ......................................45
6.4 Interrupts and Interrupt Vector ......................46
6.5 Interrupt Control ............................................48
6.6 I Flag .............................................................50
6.7 IR Bit .............................................................50
6.8 ILVL2 to ILVL0 Bits and IPL...........................50
6.9 Interrupt Sequence........................................51
6.10 Interrupt Response Time...............................52
6.11 Variation of IPL when Interrupt Request is Accepted ...... 52
6.12 Saving Registers ...........................................53
6.13 Returning from an Interrupt Routine..............55
6.14 Interrupt Priority.............................................55
6.15 Interrupt Priority Resolution Circuit ...............55
6.16 INT Interrupt ..................................................57
6.17 NMI Interrupt .................................................58
6.18 Address Match Interrupt................................58
7. WATCHDOG TIMER ..................................................60
8. DMAC ......................................................................62
8.1 Transfer Cycles .............................................67
8.2 Number of DMA Transfer Cycles ..................69
8.3 DMA Enable ..................................................70
8.4 DMA Request................................................70
8.5 Channel Priority and DMA Transfer Timing...71
9. TIMERS......................................................................72
9.1 Timer A..........................................................73
9.2 Timer B..........................................................87
10. SERIAL I/O ..............................................................93
10.1 UARTi (i=0 to 2).............................................93
10.2 Clock Synchronous serial I/O Mode............102
10.3 Clock Asynchronous Serial I/O (UART) Mode .... 109
10.4 Special Mode 1 (I2C mode)......................... 116
10.5 Special Mode 2............................................126
10.6 Special Mode 3 (IE mode)...........................131
10.7 Special Mode 4 (SIM Mode) (UART2).........133
10.8 SI/O3 and SI/O4..........................................138
11. MULTI-MASTER I2C BUS INTERFACE................143
12. A/D CONVERTER .................................................163
12.1 One-shot Mode ...........................................167
12.2 Repeat mode...............................................169
12.3 Single Sweep Mode ....................................171
12.4 Repeat Sweep Mode 0................................173
12.5 Repeat Sweep Mode 1................................175
12.6 Sample and Hold.........................................177
1. DESCRIPTION
12.7 Extended Analog Input Pins ....................... 177
12.8 External Operation Amp Connection Mode .... 177
12.9 Current Consumption Reducing Function....... 178
12.10 Analog Input Pin and External Sensor Equivalent Circuit Example .... 178
12.11 Caution of Using A/D Converter...................... 179
13. CRC CALCULATION ............................................ 180
14. EXPANSION FUNCTION ...................................... 182
14.1 Expansion function description................... 182
14.2 Expansion memory..................................... 183
14.3 slice RAM ................................................... 184
14.4 CRC Operation Circuit (EPG-J).................. 187
14.5 Expansion Register .................................... 200
14.6 Expansion Register Construction Composition... 240
14.7 8/4 Humming Decoder ............................... 247
14.8 24/18 Humming Decoder ........................... 248
14.9 I/O Composition of pins for Expansion Function. 250
15. PROGRAMMABLE I/O PORTS............................ 252
15.1 Port Pi Direction Register (PDi Register, i = 0 to 9) ..252
15.2 Port Pi Register (Pi Register, i = 0 to 9)...... 252
15.3 Pull-up Control Register 0 to Pull-up Control
Register 2 (PUR0 to PUR2 Registers) ....... 252
15.4 Port Control Register.................................. 252
16. ELECTRICAL CHARACTERISTICS .................... 263
17. FLASH MEMORY VERSION ................................ 279
17.1 Flash Memory Performance ....................... 279
17.2 Memory Map .............................................. 281
17.3 Boot Mode .................................................. 282
17.4 Functions To Prevent Flash Memory from Rewriting...282
17.5 CPU Rewrite Mode..................................... 284
17.6 Data Protect Function................................. 298
17.7 Status Register ........................................... 298
17.8 Full Status Check ....................................... 300
17.9 Standard Serial I/O Mode ........................... 302
17.10 Parallel I/O Mode........................................ 307
18. PACKAGE OUTLINE ............................................ 308
19. USEGE NOTES .................................................... 309
19.1 Precautions for Power Control ................... 309
19.2 Precautions for Protect............................... 309
19.3 Precautions for Interrupts ........................... 309
19.4 Precautions for DMAC................................ 313
19.5 Precautions for Timers ............................... 314
19.6 Precautions for Serial I/O (Clock-synchronous Serial I/O)... 317
19.7 Precautions for Serial I/O (UART Mode) .... 318
19.8 Precautions for A/D Converter ................... 318
19.9 Precautions for Programmable I/O Ports.... 318
19.10 Electric Characteristic Differences Between Mask ROM and
Flash Memory Version Microcomputers ........................ 318
19.11 Precautions for Flash Memory Version ...... 318
19.12 Other Notes ................................................ 323
19.13 Serial I/O (RxDi input setup time) ............... 325
19.14 Precautions for LP3 and LP4 pins .............. 326
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 2 of 326
Embedded System
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