R2J20601NP
Driver – MOS FET Integrated SiP (DrMOS)
REJ03G0237-0700
Rev.7.00
Jun 30, 2008
Description
The R2J20601NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in
a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier
diode (SBD), eliminating the need for an external SBD for this purpose.
Integrating a driver and both high-side and low-side power MOS FETs, the new device is also compliant with the
package standard “Driver – MOS FET integrated SiP (DrMOS)” proposed by Intel Corporation.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Built-in power MOS FET suitable for applications with 12 V input and low output voltage
Built-in driver circuit which matches the power MOS FET
Built-in tri-state input function which can support a number of PWM controllers
VIN operating-voltage range: 16 V max
High-frequency operation (above 1 MHz) possible
Large average output current (35 A)
Achieve low power dissipation (About 5.6 W at 1 MHz, 25 A)
Controllable driver: Remote on/off
Built-in Schottky diode for bootstrapping
Low-side drive voltage can be independently set
Small package: QFN56 (8 mm
×
8 mm
×
0.8 mm)
Pb-free
Outline
VCIN BOOT
GH
VIN
56
Reg5V
Driver
Tab
High-side MOS
Tab
1
14
15
DISBL#
MOS FET Driver
VSWH
Low-side MOS Tab
PWM
43
CGND VLDRV
GL
PGND
42
28
29
(Bottom view)
QFN56 package 8 mm
×
8 mm
REJ03G0237-0700 Rev.7.00 Jun 30, 2008
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R2J20601NP
Block Diagram
VCIN
Reg5V
BOOT
GH
Driver chip
UVL
DISBL#
2
µA
CGND
5 V Gen.
SBD
VIN
High-side
MOS FET
Level shifter
VSWH
VCIN
PWM
Input logic
(TTL level)
(3 state in)
Overlap
protection
Low-side
MOS FET
PGND
CGND
VLDRV
GL
Notes: 1. Truth table for the DISBL# pin.
DISBL# Input
“L”
“Open”
“H”
Driver Chip Status
Shutdown (GL, GH = “L”)
Shutdown (GL, GH = “L”)
Enable (GL, GH = “Active”)
2. Output signal from the UVL block
"H"
UVL Output
Logic Level
"L"
VL
VH
VCIN
For activation
For shutdown
REJ03G0237-0700 Rev.7.00 Jun 30, 2008
Page 2 of 13
R2J20601NP
Pin Arrangement
VLDRV
3
CGND
14
13
12
11
10
9
8
7
6
5
4
2
VIN
VIN
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
CGND
1
56
55
BOOT
VCIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
GH
NC
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
PWM
DISBL#
Reg5V
NC
GL
CGND
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VIN
CGND
54
53
52
51
50
49
48
VSWH
47
46
45
44
43
VSWH
VSWH
(Top view)
Note: All die-pads (three pads in total) should be soldered to PCB.
Pin Description
Pin Name
CGND
NC
VLDRV
VCIN
BOOT
GH
VIN
VSWH
PGND
GL
Reg5V
DISBL#
PWM
Pin No.
1, 6, 51, Tab
2, 53
3
4
5
7
8 to 20, Tab
21, 40 to 50, Tab
22 to 39
52
54
55
56
Description
Control signal ground
No connect
Low side gate supply voltage
Control input voltage (+12 V input)
Bootstrap voltage pin
High side gate signal
Input voltage
Phase output/Switch output
Power ground
Low side gate signal
+5 V logic power supply output
Signal disable
PWM drive logic input
Remarks
Should be connected to PGND externally
For 5 V to 12 V gate drive voltage for Low side
gate driver
Driver Vcc input
To be supplied +5 V through internal SBD
Pin for Monitor
Pin for Monitor
Disabled when DISBL# is “L”
REJ03G0237-0700 Rev.7.00 Jun 30, 2008
Page 3 of 13
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
R2J20601NP
Absolute Maximum Ratings
(Ta = 25°C)
Item
Power dissipation
Average output current
Input voltage
Supply voltage
Low side driver voltage
Switch node voltage
BOOT voltage
DISBL# voltage
PWM voltage
Reg5V current
Operating junction temperature
Storage temperature
Notes: 1.
2.
3.
4.
5.
6.
Symbol
Pt(25)
Pt(110)
Iout
VIN (DC)
VIN (AC)
VCIN (DC)
VCIN (AC)
VLDRV (DC)
VLDRV (AC)
VSWH (DC)
VSWH (AC)
VBOOT
Vdisble
Vpwm
Ireg5V
Tj-opr
Tstg
Rating
25
8
35
–0.3 to +16
20
–0.3 to +16
20
–0.3 to +16
20
16
20
22
–0.3 to VCIN
–0.3 to +5.3
–0.3 to +0.3
–10 to +0.1
–40 to +150
–55 to +150
Units
W
W
A
V
V
V
V
V
V
V
V
mA
°C
°C
Notes
1
1
2
2, 6
2
2, 6
2
2, 6
2
2, 6
2
2
2, 4
2, 5
3
Pt(25) represents a PCB temperature of 25°C, and Pt(100) represents 100°C.
Rated voltages are relative to voltages on the CGND and PGND pins.
For rated current, (+) indicates inflow to the chip and (–) indicates outflow.
This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode).
This rating is when UVL (Under Voltage Lock out) is effective (lock out mode).
The specification values indicated “AC” are limited within 100 ns.
Safe Operating Area
40
35
Condition
VOUT = 1.3 V
VIN = 12 V
VLDRV = 5 V
VCIN = 12 V
L = 0.45
µH
f
PWM
= 1 MHz
Average Output Current (A)
30
25
20
15
10
5
0
0
25
50
75
100
125
150
175
PCB Temperature (°C)
REJ03G0237-0700 Rev.7.00 Jun 30, 2008
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R2J20601NP
Electrical Characteristics
(Ta = 25°C, VCIN = 12 V, VLDRV = 5 V, VSWH = 0 V, unless otherwise specified)
Supply
Item
VCIN start threshold
VCIN shutdown threshold
UVLO hysteresis
VCIN bias current
VLDRV bias current
PWM
Input
PWM rising threshold
PWM falling threshold
PWM input resistance
Tri-state shutdown window
Shutdown hold-off time
Output voltage
Line regulation
Load regulation
Disable threshold
Enable threshold
Input current
Note:
Symbol
V
H
V
L
dUVL
I
CIN
I
LDRV
V
H-PWM
V
L-PWM
R
IN-PWM
V
IN-SD
t
HOLD-OFF
Vreg
Vreg-line
Vreg-load
V
DISBL
V
ENBL
I
DISBL
Min
8.1
6.5
—
10.5
31.5
3.5
0.9
30
V
L-PWM
—
4.75
–10
–10
0.9
1.9
0.5
Typ
9.0
7.2
1.8 *
1
14.0
40.7
3.8
1.2
50
—
240 *
1
5.0
0
0
1.2
2.4
2.0
Max
9.9
7.9
—
18.5
46.5
4.1
1.5
70
V
H-PWM
—
5.25
10
10
1.5
2.9
5.0
Units
V
V
V
mA
mA
V
V
kΩ
V
ns
V
mV
mV
V
V
µA
Test Conditions
V
H
– V
L
f
PWM
= 1 MHz,
t
on-PWM
= 125 ns
f
PWM
= 1 MHz,
t
on-PWM
= 125 ns
PWM = 1 V
5V
Regulator
DISBL#
Input
VCIN = 12 V to 16 V
Ireg = 0 to 10 mA
DISBL# = 1 V
1. Reference values for design. Not 100% tested in production.
REJ03G0237-0700 Rev.7.00 Jun 30, 2008
Page 5 of 13
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