a
Single and Multichannel, Synchronous
Voltage-to-Frequency Converters
AD7741/AD7742
FUNCTIONAL BLOCK DIAGRAMS
V
DD
REFIN/OUT
PD
+2.5V
REFERENCE
FEATURES
AD7741: One Single-Ended Input Channel
AD7742: Two Differential or Three Pseudo-Differential
Input Channels
Integral Nonlinearity of 0.012% at f
OUT
(Max) = 2.75 MHz
(AD7742) and at f
OUT
(Max) = 1.35 MHz (AD7741)
Single +5 V Supply Operation
Buffered Inputs
Programmable Gain Analog Front-End
On-Chip +2.5 V Reference
Internal/External Reference Option
Power Down to 35 A Max
Minimal External Components Required
8-Lead and 16-Lead DIP and SOIC Packages
APPLICATIONS
Low Cost Analog-to-Digital Conversion
Signal Isolation
GAIN
V
IN
1
V
IN
2
V
IN
3
POWER-DOWN
LOGIC
V
IN
X1
VOLTAGE-TO-
FREQUENCY
MODULATOR
f
OUT
CLOCK
GENERATION
AD7741
CLKIN
CLKOUT
GND
V
DD
UNI/BIP
PD
AD7742
POWER-DOWN
LOGIC
INPUT
MUX
X1/X2
VOLTAGE-TO-
FREQUENCY
MODULATOR
f
OUT
GENERAL DESCRIPTION
V
IN
4
A1
A0
CLOCK
GENERATION
+2.5V
REFERENCE
The AD7741/AD7742 are a new generation of synchronous
voltage-to-frequency converters (VFCs). The AD7741 is a
single-channel version in an 8-lead package (SOIC/DIP) and the
AD7742 is a multichannel version in a 16-lead package (SOIC/
DIP). No user trimming is required to achieve the specified
performance.
The AD7741 has a single buffered input whereas the AD7742
has four buffered inputs that may be configured as two fully-
differential inputs or three pseudo-differential inputs. Both parts
include an on-chip +2.5 V bandgap reference that provides the
user with the option of using this internal reference or an exter-
nal reference.
GND
CLKIN
CLKOUT
REFIN
REFOUT
The AD7741 has a single-ended voltage input range from 0 V
to REFIN. The AD7742 has a differential voltage input range
from –V
REF
to +V
REF
. Both parts operate from a single +5 V
supply consuming typically 6 mA, and also contain a power-
down feature that reduces the current consumption to less than
35
µA.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD7741–SPECIFICATIONS
Parameter
2
DC PERFORMANCE
Integral Nonlinearity
f
CLKIN
= 200 kHz
3
f
CLKIN
= 3 MHz
3
f
CLKIN
= 6.144 MHz
Offset Error
Gain Error
Offset Error Drift
3
Gain Error Drift
3
Power Supply Rejection Ratio
3
ANALOG INPUT
5
Input Current
Input Voltage Range
+2.5 V REFERENCE (REFIN/OUT)
REFIN
Nominal Input Voltage
Input Impedance
6
REFOUT
Output Voltage
Output Impedance
3
Reference Drift
3
Line Rejection
Reference Noise (0.1 Hz to 10 Hz)
3
LOGIC OUTPUT
Output High Voltage, V
OH
Output Low Voltage, V
OL
Minimum Output Frequency
Maximum Output Frequency
LOGIC INPUT
PD
ONLY
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current
Pin Capacitance
CLKIN ONLY
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current
Pin Capacitance
CLOCK FREQUENCY
Input Frequency
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
I
DD
(Power-Down)
Power-Up Time
3
4.75
(V
DD
= +4.75 V to +5.25 V; V
REF
= +2.5 V; f
CLKIN
= 6.144 MHz; all specifications T
MIN
to
T
MAX
unless otherwise noted.)
Units
Conditions/Comments
B and Y Version
1
Min
Typ
Max
0
+0.8
±
30
±
16
–63
±
50
±
0.012
±
0.012
±
0.024
±
40
+1.6
% of Span
4
% of Span
% of Span
mV
% of Span
µV/°C
ppm of Span/°C
dB
nA
V
V
DD
> 4.8 V
∆V
DD
=
±
5%
0
±
100
V
REF
2.5
N/A
2.38
2.50
1
±
50
–60
100
2.60
V
V
kΩ
ppm/°C
dB
µV
p-p
V
V
Hz
Hz
Output Sourcing 800
µA
7
Output Sinking 1.6 mA
7
V
IN
= 0 V
V
IN
= V
REF
4.0
0.4
0.05 f
CLKIN
0.45 f
CLKIN
2.4
0.8
±
100
10
6
3.5
V
V
nA
pF
V
V
µA
pF
MHz
V
mA
µA
µs
For Specified Performance
6
0.8
±
2
10
6.144
5.25
8
35
Output Unloaded
Coming Out of Power-Down Mode
15
30
NOTES
1
Temperature ranges: B Version –40°C to +85°C: Y Version: –40°C to +105°C.
2
See Terminology.
3
Guaranteed by design and characterization, not production tested.
4
Span = Maximum Output Frequency–Minimum Output Frequency.
5
The absolute voltage on the input pin must not go more positive than V
DD
– 2.25 V or more negative than GND.
6
Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400
µA
in order to overdrive the internal reference.
7
These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
Specifications subject to change without notice.
–2–
REV. 0
AD7741/AD7742
AD7742–SPECIFICATIONS
B Version
1
Parameter
3
(V
DD
= +4.75 V to +5.25 V; V
REF
= +2.5 V; f
CLKIN
= 6.144 MHz; all specifications T
MIN
to
T
MAX
unless otherwise noted.)
Y Version
2
Max
Min
Typ
Max
Units
Conditions/Comments
Min
Typ
DC PERFORMANCE
Integral Nonlinearity
f
CLKIN
= 200 kHz
4
f
CLKIN
= 3 MHz
4
f
CLKIN
= 6.144 MHz
Offset Error
Gain Error
Offset Error Drift
4
Gain Error Drift
4
Power Supply Rejection Ratio
4
Channel-to-Channel Isolation
4
Common-Mode Rejection
ANALOG INPUTS (V
IN
1–V
IN
4)
Input Current
Common-Mode Input Range
Differential Input Range
VOLTAGE REFERENCE
REFIN
Nominal Input Voltage
Input Impedance
4
f
CLKIN
= 3 MHz
f
CLKIN
= 6.144 MHz
REFOUT
Output Voltage
Output Impedance
4
Reference Drift
4
Line Rejection
Reference Noise
(0.1 Hz to 10 Hz)
4
LOGIC OUTPUT
Output High Voltage, V
OH
Output Low Voltage, V
OL
Minimum Output Frequency
Maximum Output Frequency
LOGIC INPUT
ALL EXCEPT CLKIN
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current
Pin Capacitance
CLKIN ONLY
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current
Pin Capacitance
CLOCK FREQUENCY
Input Frequency
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
I
DD
(Power-Down)
Power-Up Time
4
N
OTES
1
2
+0.2
+0.2
–60
+1.2
+1.2
±
12
±
12
±
2
±
4
–70
–75
–78
±
50
±
0.0122
±
0.0122
±
0.0122
±
40
±
40
+2.2
+2.2
+0.2
+0.2
–58
±
100
V
DD
– 1.75 +0.5
+V
REF
/Gain –V
REF
/Gain
+V
REF
/Gain 0
+1.2
+1.2
±
12
±
12
±
2
±
4
–70
–75
–78
±
50
±
0.015
±
0.015
±
0.015
±
40
±
40
+2.2
+2.2
% of Span
5
% of Span
% of Span
mV
mV
% of Span
% of Span
µV/°C
µV/°C
ppm of Span/°C
ppm of Span/°C
dB
dB
dB
nA
V
V
V
Unipolar Mode
Bipolar Mode
Unipolar Mode
Bipolar Mode
Unipolar Mode
Bipolar Mode
Unipolar Mode
Bipolar Mode
∆V
DD
=
±
5%
6
+0.5
–V
REF
/Gain
0
±
100
V
DD
– 1.75
+V
REF
/Gain
+V
REF
/Gain
Bipolar Mode
Unipolar Mode
2.5
70
35
2.38
2.50
1
±
50
–70
100
4.0
0.4
0.05 f
CLKIN
0.45 f
CLKIN
4.0
2.60
70
35
2.38
2.5
V
kΩ
kΩ
2.50
1
±
50
–70
100
2.60
V
kΩ
ppm/°C
dB
µV
p-p
V
V
Hz
Hz
Output Sourcing 800
µA
7
Output Sinking 1.6 mA
7
V
IN
= 0 V (Unipolar), V
IN
=
–V
REF
/Gain (Bipolar)
V
IN
= V
REF
/Gain (Unipolar
and Bipolar)
0.4
0.05 f
CLKIN
0.45 f
CLKIN
2.4
0.8
±
100
10
2.4
0.8
±
100
10
6
3.5
6
3.5
V
V
nA
pF
V
V
µA
pF
MHz
V
mA
µA
µs
For Specified Performance
6
0.8
±
2
10
6.144
6
0.8
±
2
10
6.144
4.75
6
25
30
5.25
8
35
4.75
6
25
30
5.25
8
35
Output Unloaded
Coming Out of Power-
Down Mode
Temperature range: B Version: –40°C to +85°C.
Temperature range: Y Version: –40°C to +105°C.
3
See Terminology.
4
Guaranteed by design and characterization, not production tested.
5
Span = Maximum Output Frequency–Minimum Output Frequency.
6
The absolute voltage on the input pins must not go more positive than V
DD
– 1.75 V or more negative than +0.5 V.
7
These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
Specifications subject to change without notice
.
REV. 0
–3–
AD7741/AD7742
TIMING CHARACTERISTICS
1, 2, 3
(V
Parameter
f
CLKIN
t
HIGH
/t
LOW
t
1
t
2
t
3
t
4
Limit at T
MIN
, T
MAX
(B and Y Version)
6.144
55/45
45/55
9
4
4
t
HIGH
±
5
DD
= +4.75 V to +5.25 V; V
REF
= +2.5 V. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Units
MHz max
max
min
ns typ
ns typ
ns typ
ns typ
Conditions/Comments
Input Clock Mark/Space Ratio
f
CLOCK
Rising Edge to f
OUT
Rising Edge
f
OUT
Rise Time
f
OUT
Fall Time
f
OUT
Pulsewidth
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 1.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1, 2
t
HIGH
CLKIN
(T
A
= +25°C unless otherwise noted)
t
4
f
OUT
t
1
t
2
t
3
Figure 1. Timing Diagram
ORDERING GUIDE
Models
AD7741BN
AD7741BR
AD7741YR
AD7742BN
AD7742BR
AD7742YR
Temperature
Ranges
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
Package
Descriptions
Plastic DIP
Small Outline
Small Outline
Plastic DIP
Small Outline
Small Outline
Package
Options
N-8
R-8
R-8
N-16
R-16A
R-16A
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . . –5 V to V
DD
+ 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
f
OUT
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +105°C
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance (8 Lead) . . . . . . . . . . . . . 125°C/W
θ
JA
Thermal Impedance (16 Lead) . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance (8 Lead) . . . . . . . . . . . . . 157°C/W
θ
JA
Thermal Impedance (16 Lead) . . . . . . . . . . . . 125°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7741/AD7742 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD7741/AD7742
AD7741 PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
Mnemonic
V
DD
GND
CLKOUT
Function
Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should
be adequately decoupled to GND.
Ground reference point for all circuitry on the part.
External Clock Output. When the master clock for the device is a crystal, the crystal is connected
between CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pin
provides an inverted clock signal. This clock should be buffered if it is to be used as a clock source
elsewhere in the system.
External Clock Input. The master clock for the device can be provided in the form of a crystal or an
external clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the
CLKIN pin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The
frequency of the master clock may be as high as 6 MHz.
This is the reference input to the core of the VFC and defines the span of the VFC. If this pin is left
unconnected, the internal 2.5 V reference is used. Alternatively, a precision external reference (e.g.,
REF192) may be used to overdrive the internal reference. The internal bandgap reference has a
high output impedance in order to allow it to be overdriven.
The analog input to the VFC. It has an input range from 0 V to V
REF
. This input is buffered so it
draws virtually no current from whatever source is driving it.
Active Low Power-Down pin. When this input is low, the part enters power-down mode where it
typically consumes 15
µA
of current.
Frequency Output. This pin provides the output of the synchronous VFC.
4
CLKIN
5
REFIN/OUT
6
7
8
V
IN
PD
f
OUT
PIN CONFIGURATION
V
DD 1
GND
2
8
f
OUT
7
PD
AD7741
TOP VIEW
CLKOUT
3
(Not to Scale)
6
V
IN
CLKIN
4
5
REFIN/OUT
REV. 0
–5–
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