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HD74LS95BFPEL

Description
4-bit Parallel Access Shift Register
Categorylogic    logic   
File Size173KB,7 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
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HD74LS95BFPEL Overview

4-bit Parallel Access Shift Register

HD74LS95BFPEL Parametric

Parameter NameAttribute value
MakerRenesas Electronics Corporation
Parts packaging codeSOIC
package instruction5.50 X 10.06 MM, 1.27 MM PITCH, PLASTIC, SOP-14
Contacts14
Reach Compliance Codecompli
Other featuresSIPO OPERATION ALSO AVAILABLE
Counting directionBIDIRECTIONAL
seriesLS
JESD-30 codeR-PDSO-G14
length10.06 mm
Logic integrated circuit typePARALLEL IN PARALLEL OUT
Number of digits4
Number of functions1
Number of terminals14
Maximum operating temperature75 °C
Minimum operating temperature-20 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
propagation delay (tpd)32 ns
Certification statusNot Qualified
Maximum seat height2.2 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL EXTENDED
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Trigger typeNEGATIVE EDGE
width5.5 mm
minfmax25 MHz
HD74LS95B
4-bit Parallel Access Shift Register
REJ03D0424-0400
Rev.4.00
May 10, 2006
The 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register
has three mode operation:
Parallel (broadside) load
Shift right (the direction Q
A
toward Q
D
)
Shift left (the direction Q
D
toward Q
A
)
Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input.
During loading, the entry of serial data is inhibited. Shift right is accomplished on the high-to-low transition of clock-1
when the mode control is low; shift left is accomplished on the high-to-low transition of clock-2 when the mode control
is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop (Q
D
to input C, etc.) and
serial data is entered at input D. The clock input may be applied commonly to clock-1 and clock-2 if both modes can be
clocked from the same source. Changes at the mode control inputs are low; however, conditions described in the last
three lines of the function table will also ensure that register contents are protected.
Features
Ordering Information
Part Name
HD74LS95BFPEL
Package Type
SOP-14 pin (JEITA)
Package Code
(Previous Code)
PRSP0014DF-B
(FP-14DAV)
Package
Abbreviation
FP
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
Pin Arrangement
Serial Input
A
B
Inputs
C
D
Mode Control
GND
1
2
3
4
5
6
7
Serial Input
A
Q
A
B
C
D
Mode
Q
B
Q
C
Q
D
CK
1
CK
2
14
13
12
11
10
9
8
V
CC
Q
A
Q
B
Outputs
Q
C
Q
D
Clock1
R-Shift
Clock2
L-Shift (Load)
(Top view)
Rev.4.00, May 10, 2006, page 1 of 6

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