REJ09B0015-0200Z
32
32171 Group
User’s Manual
RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER
M32R FAMILY / M32R/ECU SERIES
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 2.00
Revision date: Sep 19, 2003
www.renesas.com
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REVISION HISTORY
Rev.
0.1
1.0
Date
Page
Apr 8, 2000
Nov 1, 2002
all
all
P1-6
32171 Group User’s Manual
Description
Summary
–
First edition issued
Explanation of the M32171F2 added
Designation of M32R/E changed to M32R/ECU
Description in Section 1.1.6, Built-in Full-CAN Function, corrected
Incorrect: Compliant with CAN Specification V2.0B
Correct: Compliant with CAN Specification V2.0B active
P1-7
P1-8
P1-10
P1-11
M32171F2 added to the internal flash memory in Figure 1.2.1
M32171F2 added to the internal flash memory in Table 1.2.2
Table 1.2.4, List of Type Name added
Note 1 in Figure 1.3.1 corrected
Incorrect: Operates with a 5 V power supply
Correct: Operates with a 3.3 V or 5 V power supply
P1-12
Functional description of pin names VCCE and OSC-VCC in Table 1.3.1corrected
Explanation of WR added to the functional description of clock in Table 1.3.1
P1-13
P1-17
P3-5
P3-6
Explanation of the A-D converter in Table 1.3.1 corrected
Figure 1.4.1 corrected
Figure 3.1.3, "M32171F2 address space," added
Table 3.2.1 corrected
Note 1 in Table 3.2.1 corrected
P3-7
P3-8
P4-25
P5-13
P5-17
P5-19
P6-2
Figure 3.2.3 "M32171F2 operation mode and internal ROM/external extended areas,"
added
M32171F2 added to Table 3.3.1
Section 4.13, "Precautions on EIT," added
Relevant names of causes added to Table 5.4.1
Relevant names of causes added to Table 5.5.1
Explanation added to (4) "Enabling multiple interrupts" in Section 5.5.2, "Processing of
Internal Peripheral I/O Interrupts by Handler"
Description in Section 6.1, "Outline of the Internal Memory," corrected
Precautions added to Table 6.2.1
P6-3
P6-5
P6-7
P6-8
P6-13
P6-22
P6-25
M32171F2 added to Table 6.3.1
Precautions added
Precautions (Note 2) added
Precautions added
Figure 6.4.4, “FCNT4 Register Usage Example 2,” added
Table 6.5.1 corrected
Precautions (Note 2, 3, 4) added to Table 6.5.2
(1/8)
REVISION HISTORY
Rev.
1.0
Date
Page
Nov 1, 2002 P6-27
P6-30
P6-38
P6-40
P6-43
P6-46
32171 Group User’s Manual
Description
Summary
Table 6.5.5, “M32171F2’s relevant block and specificaion address,” added
Table 6.5.9, “Block configuration of M32171F2 flash memory,” added
Figure 6.5.15, Figure 6.5.16 and Figure 6.5.17 corrected
(3) M32171F2 added to Section 6.5.4, “Flash Programming Time (Reference Value)”
Precautios (Notes 2, 3, 4) added
Figure 6.7.6, “Virtual-flash emulation area of the M32171F2 divided in 8 Kbyte units,”
added
Figure 6.7.7, “Virtual-flash emulation area of the M32171F2 divided in 4 Kbyte units,”
added
P6-47,
P6-48
P6-49
Incorrect register names in Figures 6.7.8 through 6.7.11 corrected
Incorrect: LBAKNKAD
Correct: LBANKAD
Figure 6.7.12, “Virtual-flash bank register setup values for the M32171F2 when divided in
8 Kbyte units,” added
Figure 6.7.13, “Virtual-flash bank register setup values for the M32171F2 when divided in
4 Kbyte units,” added
P6-55
P6-56
P7-3
P7-4
to P7-7
P8-4
Section 6.9, “Internal Flash Memory Protect Functions,” added
Explanation in Section 6.10, ”Precautions to Be Taken when Reprogramming Flash
Memory,” changed
Table 7.3.1 corrected
Tables 7.3.2 to 7.3.5, “ Pin Status When Reset,” added or corrected
Table 8.2.1 corrected
Precautions in Table 8.2.1 corrected
P8-22
to P8-25
P8-26
P9-4
P10-1 to
P10-142
P10-4
P10-5
P10-12
P10-31
P10-47
P10-55
P10-66
Figures 8.4.1 to 8.4.4 corrected
Section 8.5, “Precautions on Input/output Ports,” added
Figure 9.1.2, “Causes of DMAC Requests Connection Diagram,” added
Chapter 10 overall, designation of the prescaler unified to PRS
Port numbers added to Figure 10.1.1
Port numbers added to Figure 10.1.2
Port numbers added to Figure 10.2.2
Figure 10.2.5 changed
Port numbers added to Figure 10.3.1
Port number added to Figure 10.3.5
Figure 10.3.8 corrected
(2/8)
REVISION HISTORY
Rev.
1.0
Date
Page
Nov 1, 2002
P10-84
P10-93
P10-96
P10-124
P10-130
P10-133
P10-141
P11-3
32171 Group User’s Manual
Description
Summary
Port numbers added to Figure 10.4.1
Port numbers added to Figure 10.4.5
Port numbers added to Figure 10.4.6
Port numbers added to Figure 10.5.1
Figure 10.5.3 corrected
Port numbers added to Figure 10.6.1
Note 1 in Figure 10.6.3 corrected
Table 11.1.1 corrected
Precautions in Table 11.1.1 corrected
P11-4
P11-35
Register names in Figure 11.1.1 corrected
Method for calculating the conversion time during A-D conversion mode and that for
conversion time during comparate mode explained separately
Table 11.3.1 and precausions corrected
Figure 11.3.4, “Conceptual Diagram of Conversion Time in Comparate Mode,” added
Table 11.3.2, “Conversion Clock Cycles in Comparate Mode,” added
P11-37
to P11-38
P11-40
P12-12
P12-24
Explanation in Section 11.3.5, “Definition of the A-D Conversion Accuracy,” changed
A section “Regarding the analog input pins” added to Section 11.4, “Precautions on Using
Figure 12.2.4 corrected
Description of the last line in Section 12.2.8, “SIO Baud Rate Register,” corrected
Incorrect: 7 or less
Correct: greater than 7
to P11-42 A-D Converters”
P12-58
Figure 12.7.5, “Detecting the Start Bit, added
Figure 12.7.6, “Example of an Invalid Start Bit (Not Received),” added
Figure 12.7.7, “Delay when Receiving,” added
P13-2
Description in Section 13.1, “Outline of the CAN Module,” corrected
Incorrect: Compliant with CAN (Controller Area Network) Specification V2.0B
Correct: Compliant with CAN (Controller Area Network) Specification V2.0B active
Protocol explanation in Table 13.1.1 corrected
Incorrect: CAN Specification V2.0B
Correct: CAN Specification V2.0B active
Explanation of acceptance filters in Table 13.1.1 changed
Precautions in Table 13.1.1 changed
P13-3
P13-19
P13-20
Figure 13.1.1 corrected
Table 13.2.2, “Example for Setting Bit Timing when CPU Clock: 32 MHz,” added
Note 3 added
(3/8)
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