S71WS256ND0BAWE71 datasheet, PDF

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S71WS256ND0BAWE71: DescriptionMemory Circuit, 16MX16, CMOS, PBGA84, 9 X 12 MM, 1.20 MM HEIGHT, FBGA-84; Categorystorage storage; File Size3MB，144 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/

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S71WS256ND0BAWE71 Overview

Memory Circuit, 16MX16, CMOS, PBGA84, 9 X 12 MM, 1.20 MM HEIGHT, FBGA-84

S71WS256ND0BAWE71 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	84
Reach Compliance Code	compliant
Other features	PSRAM IS ORGANIZED AS 8M X 16BIT; SYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE
JESD-30 code	R-PBGA-B84
JESD-609 code	e0
length	12 mm
memory density	268435456 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	84
word count	16777216 words
character code	16000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	16MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	9 mm
Base Number Matches	1

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S71WS512Nx0/S71WS256Nx0 Based MCPs

Stacked Multi-chip Product (MCP)

256/512 Megabit (32M/16M x 16 bit) CMOS

1.8 Volt-only Simultaneous Read/Write,

Burst-mode Flash Memory with

128 Megabit (8M x 16-Bit) pSRAM Type 4

ADVANCE

INFORMATION

Distinctive Characteristics

MCP Features

Power supply voltage of 1.7 to 1.95V

Burst Speed: 54MHz

Packages: 8 x 11.6 mm, 9 x 12 mm

Operating Temperature

-25°C to +85°C

-40°C to +85°C

General Description

The S71WS Series is a product line of stacked Multi-chip Product (MCP) packages

and consists of

One or more flash memory die

pSRAM Type 4—Compatible pSRAM

The products covered by this document are listed in the table below. For details

about their specifications, please refer to the individual constituent datasheet for

further details.

Flash Density

512Mb

pSRAM Density

128Mb

64Mb

32Mb

16Mb

S71WS512ND0

256Mb

S71WS256ND0

128Mb

64Mb

Publication Number

S71WS512/256Nx0_UT

Revision

Amendment

Issue Date

November 8, 2004

A d v a n c e

I n f o r m a t i o n

S71WS512Nx0/S71WS256Nx0 Based MCPs

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1

MCP Features ................................................................................................... 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . 1

bProduct Selector Guide . . . . . . . . . . . . . . . . . . . . .5

MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7

Type 4 - based Pinout ..........................................................................................7

MCP Look-ahead Connection Diagram .........................................................8

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . .9

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10

Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . 11

256Mb - WS256N Flash + 128 pSRAM .......................................................... 11

2x256Mb—WS256N Flash + 128Mb pSRAM ............................................... 11

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12

FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP

Compatible Package ........................................................................................... 12

TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP

Compatible Package ............................................................................................13

TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6x8.0x1.2 mm

MCP Compatible Package ................................................................................14

S29WSxxxN MirrorBit™ Flash Family

General Description . . . . . . . . . . . . . . . . . . . . . . . 15

Application Notes ........................................................................................... 18

Specification Bulletins .................................................................................... 18

Drivers and Software Support .................................................................... 18

CAD Modeling Support ................................................................................ 18

Technical Support ........................................................................................... 18

Spansion LLC Locations ........................................................ 18

Table 4.2. S29WS128N Sector & Memory Address Map .......... 20

Table 4.3. S29WS064N Sector & Memory Address Map .......... 21

Table 5.4. Device Operations .............................................. 22

Table 5.7. Address Latency for 5 Wait States (≤ 68 MHz) ........ 24

Table 5.8. Address Latency for 4 Wait States (≤ 54 MHz) ........ 25

Table 5.9. Address Latency for 3 Wait States (≤ 40 MHz) ........ 25

Table 5.10. Address/Boundary Crossing Latency for 6 Wait States

(≤ 80 MHz) ....................................................................... 25

Table 5.11. Address/Boundary Crossing Latency for 5 Wait States

(≤ 68 MHz) ....................................................................... 25

Table 5.12. Address/Boundary Crossing Latency for 4 Wait States

(≤ 54 MHz) ....................................................................... 25

Table 5.13. Address/Boundary Crossing Latency for 3 Wait States

(≤ 40 MHz) ....................................................................... 25

Figure 5.2. Synchronous Read ............................................. 26

Table 5.14. Burst Address Groups ....................................... 27

Table 5.15. Configuration Register ....................................... 28

Table 5.16. Autoselect Addresses ........................................ 29

Table 5.17. Autoselect Entry ............................................... 29

Table 5.18. Autoselect Exit ................................................. 30

Figure 5.19. Single Word Program ........................................ 32

Table 5.20. Single Word Program ........................................ 33

Table 5.21. Write Buffer Program ........................................ 35

Figure 5.22. Write Buffer Programming Operation .................. 36

Table 5.23. Sector Erase .................................................... 38

Figure 5.24. Sector Erase Operation ..................................... 39

Table 5.25. Chip Erase ....................................................... 40

Table 5.26. Erase Suspend ................................................. 41

Table 5.27. Erase Resume .................................................. 41

Table 5.28. Program Suspend ............................................. 42

Table 5.29. Program Resume .............................................. 42

Table 5.30. Unlock Bypass Entry .......................................... 43

Table 5.31. Unlock Bypass Program ..................................... 44

Table 5.32. Unlock Bypass Reset ......................................... 44

Figure 5.33. Write Operation Status Flowchart....................... 46

Table 5.34. DQ6 and DQ2 Indications ................................... 48

Table 5.35. Write Operation Status ...................................... 49

Table 5.36. Reset .............................................................. 51

Figure 6.2. Lock Register Program Algorithm......................... 57

Table 8.2. SecSi Sector Entry .............................................. 63

Table 8.3. SecSi Sector Program .......................................... 64

Table 8.4. SecSi Sector Entry .............................................. 64

Figure 9.2. Maximum Positive Overshoot Waveform ............... 65

Figure 9.3. Test Setup........................................................ 66

Figure 9.4. Input Waveforms and Measurement Levels ........... 67

Figure 9.5. V

Power-up Diagram....................................... 67

Figure 9.6. CLK Characterization.......................................... 69

Figure 9.7. CLK Synchronous Burst Mode Read...................... 71

Figure 9.8. 8-word Linear Burst with Wrap Around................. 72

Figure 9.9. 8-word Linear Burst without Wrap Around ............ 72

Figure 9.10. Linear Burst with RDY Set One Cycle Before Data 73

Figure 9.11. Asynchronous Mode Read ................................. 74

Figure 9.12. Reset Timings ................................................. 75

Figure 9.2. Chip/Sector Erase Operation Timings: WE# Latched

Addresses......................................................................... 77

Figure 9.13. Asynchronous Program Operation Timings: WE#

Latched Addresses............................................................. 78

Figure 9.14. Synchronous Program Operation Timings:

CLK Latched Addresses ...................................................... 79

Figure 9.15. Accelerated Unlock Bypass Programming Timing.. 80

Figure 9.16. Data# Polling Timings

(During Embedded Algorithm)............................................. 80

Figure 9.17. Toggle Bit Timings (During Embedded Algorithm) 81

Figure 9.18. Synchronous Data Polling

Timings/Toggle Bit Timings ................................................. 81

Figure 9.19. DQ2 vs. DQ6................................................... 82

Figure 9.20. Latency with Boundary Crossing when

Frequency > 66 MHz.......................................................... 82

Figure 9.21. Latency with Boundary Crossing into Program/

Erase Bank ....................................................................... 83

Figure 9.22. Example of Wait States Insertion ....................... 84

Figure 9.23. Back-to-Back Read/Write Cycle Timings.............. 85

Table 10.2. Sector Protection Commands .............................. 90

Table 10.3. CFI Query Identification String ............................ 91

Table 10.4. System Interface String ..................................... 92

Table 10.5. Device Geometry Definition ................................ 92

Table 10.6. Primary Vendor-Specific Extended Query ............. 93

pSRAM Type 4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 99

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 100

Power Up ............................................................................................................ 100

Figure 11.24. Power Up Timing.......................................... 100

Standby Mode .................................................................................................... 100

Figure 11.25. Standby Mode State Machines ....................... 100

Functional Description . . . . . . . . . . . . . . . . . . . . . 101

Table 11.7. Asynchronous 4 Page Read & Asynchronous Write Mode

(A15/A14=0/0) ............................................................... 101

Table 11.8. Synchronous Burst Read & Asynchronous Write Mode

(A15/A14=0/1) ............................................................... 102

Table 11.9. Synchronous Burst Read & Synchronous Burst Write

Mode(A15/A14=1/0) ........................................................ 103

Mode Register Setting Operation . . . . . . . . . . . . 103

November 8, 2004 S71WS512/256Nx0_UTA0

S71WS512Nx0/S71WS256Nx0

A d v a n c e

I n f o r m a t i o n

Mode Register Set (MRS) ...............................................................................104

Table 11.10. Mode Register Setting According to

Field of Function ...............................................................104

Table 11.11. Mode Register Set ..........................................104

Figure 11.39. Timing Waveform Of Write Cycle (Address Latch

Type)............................................................................. 121

Table 11.21. Asynchronous Write in Synchronous Mode AC

Characteristics ................................................................ 121

MRS Pin Control Type Mode Register Setting Timing .......................... 105

Figure 11.26. Mode Register Setting Timing (OE# = V

) ...... 106

Table 11.12. MRS AC Characteristics ...................................106

Asynchronous Write Timing Waveform in Synchronous Mode ........122

Write Cycle (Low ADV# Type) ...............................................................122

Figure 11.40. Timing Waveform Of Write

Cycle (Low ADV# Type).................................................... 122

Table 11.22. Asynchronous Write in Synchronous Mode AC

Characteristics ................................................................ 122

Asynchronous Operation . . . . . . . . . . . . . . . . . . 107

Asynchronous 4 Page Read Operation ...................................................... 107

Asynchronous Write Operation .................................................................. 107

Asynchronous Write Operation in Synchronous Mode ....................... 107

Figure 11.27. Asynchronous 4-Page Read............................ 107

Figure 11.28. Asynchronous Write ...................................... 107

Write Cycle (Low ADV# Type) ...............................................................123

Figure 11.41. Timing Waveform Of Write Cycle

(Low ADV# Type) ............................................................ 123

Table 11.23. Asynchronous Write in Synchronous Mode AC

Characteristics ................................................................ 123

Synchronous Burst Operation . . . . . . . . . . . . . . 108

Synchronous Burst Read Operation ...........................................................108

Synchronous Burst Write Operation .........................................................108

Figure 11.29. Synchronous Burst Read................................ 108

Figure 11.30. Synchronous Burst Write ............................... 109

Multiple Write Cycle (Low ADV# Type) ..............................................124

Figure 11.42. Timing Waveform Of Multiple Write Cycle (Low ADV#

Type)............................................................................. 124

Table 11.24. Asynchronous Write in Synchronous Mode AC

Characteristics ................................................................ 125

Synchronous Burst Operation Terminology . . 109

Clock (CLK) ........................................................................................................109

Latency Count ....................................................................................................109

Table 11.13. Latency Count Support ...................................109

Table 11.14. Number of CLocks for 1st Data ........................109

Figure 11.31. Latency Configuration (Read) ......................... 110

AC Operating Conditions . . . . . . . . . . . . . . . . . . 126

Test Conditions (Test Load and Test Input/Output Reference) ........126

Figure 11.43. AC Output Load Circuit ................................. 126

Table 11.25. Synchronous AC Characteristics ..................... 127

Burst Length ........................................................................................................110

Burst Stop .............................................................................................................110

Synchronous Burst Operation

Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 11.44. Timing Waveform Of Basic Burst Operation ..... 128

Table 11.26. Burst Operation AC Characteristics .................. 128

Synchronous Burst Operation Terminology . . . 110

Wait Control (WAIT#) ...................................................................................110

Figure 11.32. WAIT# and Read/Write Latency Control........... 111

Synchronous Burst Read Timing Waveform . . . 129

Read Timings .......................................................................................................129

Figure 11.45. Timing Waveform of Burst Read Cycle (1) ....... 129

Table 11.27. Burst Read AC Characteristics ......................... 130

Figure 11.46. Timing Waveform of Burst Read Cycle (2) ....... 130

Table 11.28. Burst Read AC Characteristics ......................... 131

Figure 11.47. Timing Waveform of Burst Read Cycle (3) ....... 131

Table 11.29. Burst Read AC Characteristics ......................... 132

Burst Type ............................................................................................................. 111

Table 11.15. Burst Sequence .............................................111

Low Power Features . . . . . . . . . . . . . . . . . . . . . . 112

Internal TCSR ...................................................................................................... 112

Figure 11.33. PAR Mode Execution and Exit ......................... 112

Table 11.16. PAR Mode Characteristics ................................112

Driver Strength Optimization ........................................................................ 112

Partial Array Refresh (PAR) mode ............................................................... 112

Write Timings ..................................................................................................... 133

Figure 11.48. Timing Waveform of Burst Write Cycle (1)....... 133

Table 11.30. Burst Write AC Characteristics ........................ 134

Figure 11.49. Timing Waveform of Burst Write Cycle (2)....... 135

Table 11.31. Burst Write AC Characteristics ........................ 135

Absolute Maximum Ratings . . . . . . . . . . . . . . . . .

DC Recommended Operating Conditions . . . . .

Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . . .

DC and Operating Characteristics . . . . . . . . . . .

113

114

Common ............................................................................................................... 114

Synchronous Burst Read Stop

Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 11.50. Timing Waveform of Burst Read Stop by CS#.. 136

Table 11.32. Burst Read Stop AC Characteristics ................. 136

AC Operating Conditions . . . . . . . . . . . . . . . . . . 115

Test Conditions (Test Load and Test Input/Output Reference) ........ 115

Figure 11.34. Output Load................................................. 115

Asynchronous AC Characteristics ............................................................... 116

Synchronous Burst Write Stop

Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 11.51. Timing Waveform of Burst Write Stop by CS#.. 137

Table 11.33. Burst Write Stop AC Characteristics ................. 137

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 117

Asynchronous Read Timing Waveform ...................................................... 117

Figure 11.35. Timing Waveform Of Asynchronous Read Cycle 117

Table 11.17. Asynchronous Read AC Characteristics .............117

Synchronous Burst Read Suspend Timing

Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 11.52. Timing Waveform of Burst

Read Suspend Cycle (1) ................................................... 138

Table 11.34. Burst Read Suspend AC Characteristics ............ 138

Page Read .........................................................................................................118

Figure 11.36. Timing Waveform Of Page Read Cycle ............. 118

Table 11.18. Asynchronous Page Read AC Characteristics ......118

Asynchronous Write Timing Waveform .................................................... 119

Figure 11.37. Timing Waveform Of Write Cycle .................... 119

Table 11.19. Asynchronous Write AC Characteristics .............119

Transition Timing Waveform Between Read And

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 11.53. Synchronous Burst Read to Asynchronous Write

(Address Latch Type) ....................................................... 139

Table 11.35. Burst Read to Asynchronous Write (Address Latch

Type) AC Characteristics ................................................... 139

Figure 11.54. Synchronous Burst Read to Asynchronous Write (Low

ADV# Type).................................................................... 140

Table 11.36. Burst Read to Asynchronous Write (Low ADV# Type)

Write Cycle 2 ................................................................................................120

Figure 11.38. Timing Waveform of Write Cycle(2)................. 120

Table 11.20. Asynchronous Write AC Characteristics (UB# & LB#

Controlled) ......................................................................120

Write Cycle (Address Latch Type) .......................................................... 121

S71WS512Nx0/S71WS256Nx0

S71WS512/256Nx0_UTA0 November 8, 2004

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