TC74AC74P/F/FT
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74AC74P, TC74AC74F, TC74AC74FT
Dual D-Type Flip Flop with Preset and Clear
The TC74AC74 is an advanced high speed CMOS D-FLIP
FLOP fabricated with silicon gate and double-layer metal wiring
C
2
MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The signal level applied to the D INPUT is transferred to Q
OUTPUT during the positive going transition of the CK pulse.
CLR
and
PR
are independent of the CK and are
accomplished by setting the appropriate input to an “L” level.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
TC74AC74P
TC74AC74F
Features
•
•
•
•
High speed: f
max
= 200 MHz (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 4
μA
(max) at Ta = 25°C
High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
Symmetrical output impedance: |I
OH
| = I
OL
= 24 mA (min)
Capability of driving 50
Ω
transmission lines.
Balanced propagation delays: t
pLH
∼
t
pHL
−
Wide operating voltage range: V
CC (opr)
= 2 V to 5.5 V
Pin and function compatible with 74F74
TC74AC74FT
•
•
•
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
TSSOP14-P-0044-0.65A
: 0.96 g (typ.)
: 0.18 g (typ.)
: 0.06 g (typ.)
Start of commercial production
1986-05
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2014-03-01
TC74AC74P/F/FT
Pin Assignment
IEC Logic Symbol
1PR
1CK
1D
1CLR
2PR
2CK
2D
2CLR
(4)
(3)
(2)
(1)
(10)
(11)
(12)
(13)
S
C1
1D
R
(5)
(6)
(9)
(8)
1CLR
1D
1CK
1PR
1
2
3
4
5
6
7
(top view)
CK
Q
D
Q
CK
Q
D
Q
14
13
12
11
10
9
8
V
CC
1Q
2CLR
2D
2CK
2PR
2Q
1Q
2Q
2Q
1Q
1Q
GND
2Q
Truth Table
Inputs
Outputs
CLR
L
H
L
H
H
H
PR
H
L
L
H
H
H
D
X
X
X
L
H
X
CK
X
X
X
Q
L
H
H
L
H
Q
n
Q
H
L
H
H
L
Q
n
Function
Clear
Preset
―
―
―
No Change
X: Don’t care
System Diagram
1/13
4/10
6/8
Q
CLR
PR
D
2/12
ϕ
5/9
Q
φ
φ
ϕ
CK
3/11
φ
ϕ
2
2014-03-01
TC74AC74P/F/FT
Absolute Maximum Ratings (Note 1)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
−0.5
to 7.0
−0.5
to V
CC
+ 0.5
−0.5
to V
CC
+ 0.5
±20
±50
±50
±100
500 (DIP) (Note 2)/180 (SOP/TSSOP)
−65
to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta =
−40°C
to 65°C. From Ta = 65°C to 85°C, a derating factor of
−10
mW/°C
should be applied up to 300 mW.
Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall time
Symbol
V
CC
V
IN
V
OUT
T
opr
dt/dV
Rating
2.0 to 5.5
0 to V
CC
0 to V
CC
−40
to 85
0 to 100 (V
CC
= 3.3 ± 0.3 V)
0 to 20 (V
CC
= 5 ± 0.5 V)
Unit
V
V
V
°C
ns/V
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either V
CC
or GND.
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2014-03-01
TC74AC74P/F/FT
Electrical Characteristics
DC Characteristics
Test Condition
Characteristics
Symbol
V
CC
(V)
2.0
High-level input
voltage
V
IH
―
3.0
5.5
2.0
Low-level input
voltage
V
IL
―
3.0
5.5
2.0
I
OH
=
−50 μA
High-level output
voltage
V
OH
V
IN
= V
IH
or
I
OH
=
−4
mA
V
IL
I
OH
=
−24
mA
I
OH
=
−75
mA
(Note)
3.0
4.5
3.0
4.5
5.5
2.0
I
OL
= 50
μA
Low-level output
voltage
V
OL
V
IN
= V
IH
or
I
OL
= 12 mA
V
IL
I
OL
= 24 mA
I
OL
= 75 mA
Input leakage
current
Quiescent supply
current
I
IN
I
CC
V
IN
= V
CC
or GND
V
IN
= V
CC
or GND
(Note)
3.0
4.5
3.0
4.5
5.5
5.5
5.5
Min
1.50
2.10
3.85
―
―
―
1.9
2.9
4.4
2.58
3.94
―
―
―
―
―
―
―
―
―
Ta = 25°C
Typ.
―
―
―
―
―
―
2.0
3.0
4.5
―
―
―
0.0
0.0
0.0
―
―
―
―
―
Max
―
―
―
0.50
0.90
1.65
―
―
―
―
―
―
0.1
0.1
0.1
0.36
0.36
―
±0.1
4.0
Ta =
−40
to 85°C
Min
1.50
2.10
3.85
―
―
―
1.9
2.9
4.4
2.48
3.80
3.85
―
―
―
―
―
―
―
―
Max
―
―
―
0.50
0.90
1.65
―
―
―
―
―
―
0.1
0.1
0.1
0.44
0.44
1.65
±1.0
40.0
μA
μA
V
V
V
V
Unit
Note:
This spec indicates the capability of driving 50
Ω
transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
Timing Requirements (input: t
r
= t
f
= 3 ns)
Characteristics
Symbol
Test Condition
V
CC
(V)
Minimum pulse width
(CK)
Minimum pulse width
( CLR , PR )
Minimum set-up time
t
w (L)
t
w (H)
t
w (L)
―
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
Ta =
25°C
Limit
7.0
5.0
7.0
5.0
6.0
3.5
1.0
1.0
4.0
2.0
Ta =
−40
to
85°C
Limit
7.0
5.0
7.0
5.0
6.0
3.5
1.0
1.0
4.0
2.0
ns
Unit
―
ns
t
s
―
ns
Minimum hold time
Minimum removal time
( CLR , PR )
t
h
―
ns
t
rem
―
ns
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2014-03-01
TC74AC74P/F/FT
AC Characteristics
(C
L
= 50 pF, R
L
= 500
Ω,
input: t
r
= t
f
= 3 ns)
Characteristics
Propagation delay
time
(CK-Q, Q )
Propagation delay
time
(
CLR
, PR -Q,
Q
)
Maximum clock
frequency
Input capacitance
Power dissipation
capacitance
Symbol
Test Condition
V
CC
(V)
t
pLH
t
pHL
t
pLH
t
pHL
f
max
C
IN
C
PD
―
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
―
(Note)
Min
―
―
―
―
60
100
―
―
Ta = 25°C
Typ.
8.2
6.1
8.0
5.7
120
160
5
77
Max
13.9
8.7
13.1
8.2
―
―
10
―
Ta =
−40
to 85°C
Min
1.0
1.0
1.0
1.0
60
100
―
―
Max
16.0
10.0
15.0
9.4
―
―
10
―
ns
Unit
―
ns
―
MHz
pF
pF
Note:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr)
= C
PD
·V
CC
·f
IN
+ I
CC
/2 (per F/F)
5
2014-03-01
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