RFF70N06
Data Sheet
March 1999
File Number
4073.2
25A, 60V, 0.025 Ohm, N-Channel Power
MOSFET
Title
FF7
06)
b-
t
A,
V,
25
m,
Cha
el
wer
OS-
T)
utho
ey-
rds
ter-
rpo-
on,
A,
V,
25
m,
Cha
el
wer
OS-
T,
-
4AA
e-
r ()
OCI
O
f-
The RFF70N06 N-Channel power MOSFET is manufactured
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits gives
optimum utilization of silicon, resulting in outstanding
performance. It was designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.
Reliability screening is available as either commercial or
TX/TXV equivalent of MIL-S-19500. Contact Intersil
Corporation High-Reliability Marketing group for any desired
deviations from the data sheet.
Formerly developmental type TA49007.
Features
• 25A
†
, 60V
• r
DS(ON)
= 0.025
Ω
• Temperature Compensating PSPICE™ Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 150
o
C Operating Temperature
• Reliability Screened
†
Current is limited by the package capability.
Symbol
D
Ordering Information
PART NUMBER
RFF70N06
PACKAGE
TO-254AA
BRAND
RFF70N06
G
S
NOTE: When ordering, use the entire part number.
Commercial Version: RFG70N06.
Packaging
JEDEC TO-254AA
GATE
SOURCE
DRAIN
PACKAGE TAB
(ISOLATED)
CAUTION: Berylia Warning per MIL-S-19500.
Refer to package specifications.
©2001 Fairchild Semiconductor Corporation
RFF70N06 Rev. A
RFF70N06
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Continuous Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 4) (Figure 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Single Pulse Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
D
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
RFF70N06
60
60
±
20
25 (Note 2)
Refer to Peak Current Curve
Refer to UIS Curve
100
0.80
-55 to 150
260
UNITS
V
V
V
A
W
W/
o
C
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
2. Current is limited by the package capability.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
TEST CONDITIONS
I
D
= 250
µ
A, V
GS
= 0V
V
GS
= V
DS
, I
D
= 250
µ
A
V
DS
= Rated BV
DSS,
V
GS
= 0V
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
C
= 125
o
C
V
GS
=
±
20V, T
C
= 125
o
C
I
D
= 25A, V
GS
= 10V
V
DD
= 30V, I
D
≈
25A, R
L
= 1.2
Ω
,
V
GS
= 10V, R
GS
= 2.35
Ω
(Figures 13, 16, 17)
MIN
60
2.0
-
-
-
-
-
-
-
-
-
-
V
GS
= 0 to 20V
V
GS
= 0 to 10V
V
GS
= 0 to 2V
V
DD
= 30V, I
D
= 25A,
R
L
= 1.2
Ω
I
G(REF)
= 1.0mA
(Figures 18, 19)
-
-
-
-
-
-
-
-
TYP
-
3.0
-
-
-
-
-
25
70
60
25
-
-
-
-
3100
900
300
-
-
MAX
-
4.5
25
250
±
100
0.025
240
70
170
150
65
215
260
145
7
-
-
-
1.25
48
UNITS
V
V
µ
A
µ
A
µΑ
Ω
ns
ns
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 3)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
I
GSS
r
DS(ON)
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Q
g(TOT)
Q
g(10)
Q
g(TH)
C
ISS
C
OSS
C
RSS
R
θ
JC
R
θ
JA
V
DS
= 25V, V
GS
= 0V, f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Diode Reverse Recovery Time
NOTES:
3. Pulse test: pulse width
≤
300ms, duty cycle
≤
2%.
4. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Impedance curve Figure 3).
SYMBOL
V
SD
t
rr
I
SD
= 25A
I
SD
= 25A, dI
SD
/dt = 100A/
µ
s
TEST CONDITIONS
MIN
-
-
TYP
1.1
190
MAX
1.5
300
UNITS
V
ns
©2001 Fairchild Semiconductor Corporation
RFF70N06 Rev. A
RFF70N06
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
T
C
, CASE TEMPERATURE (
o
C)
125
150
I
D
, DRAIN CURRENT (A)
Unless Otherwise Specified
30
25
20
15
10
5
0
25
50
75
100
125
150
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
THERMAL IMPEDANCE
Z
θ
JC
, NORMALIZED
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
10
-5
SINGLE PULSE
10
-4
10
-3
10
-2
10
-1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JC
x R
θ
JC
+ T
C
10
0
10
1
t, RECTANGULAR PULSE DURATION (s)
P
DM
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
T
C
= 25
o
C
I
DM
, PEAK CURRENT (A)
I
D
, DRAIN CURRENT (A)
10
3
FOR TEMPERATURES ABOVE 25
o
C
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
100
100µs
150
–
T C
I
=
I 25
---------------------
125
10
2
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
V
DSS
MAX = 60V
10ms
100ms
DC
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
V
GS
= 10V
T
C
= 25
o
C
10
1
10
-5
10
-4
10
-3
10
-2
10
-1
t, PULSE WIDTH (s)
10
0
10
1
1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
RFF70N06 Rev. A
RFF70N06
Typical Performance Curves
300
I
AS
, AVALANCHE CURRENT (A)
150
100
75
STARTING T
J
= 150
o
C
I
D
, DRAIN CURRENT (A)
125
100
75
50
V
GS
= 4.5V
V
GS
= 5V
V
GS
= 10V
V
GS
= 20V
V
GS
= 7V
Unless Otherwise Specified
(Continued)
STARTING T
J
= 25
o
C
10
250µs PULSE TEST
T
C
= 25
o
C
V
GS
= 6V
1
0.01
If R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R) ln [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
0.1
1
10
100
t
AV
, TIME IN AVALANCHE (ms)
1000
25
0
0
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
2
4
6
8
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10
FIGURE 7. SATURATION CHARACTERISTICS
I
DS(ON)
, DRAIN TO SOURCE CURRENT (A)
150
125
100
V
DD
= 15V
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
-55
o
C
25
o
C
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.5
PULSE DURATION = 250µs
V
GS
= 10V,
I
D
= 25A
2.0
150
o
C
75
50
25
0
0
2
4
6
8
V
GS
, GATE TO SOURCE VOLTAGE (V)
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0
V
GS
= V
DS
, I
D
= 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
2.0
I
D
= 250µA
1.5
THRESHOLD VOLTAGE
NORMALIZED GATE
1.5
1.0
1.0
0.5
0.5
0
-80
-40
0
40
80
120
160
0
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
RFF70N06 Rev. A
RFF70N06
Typical Performance Curves
5000
V
GS
= 0V, f = 0.1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
≈
C
DS
+ C
GS
Unless Otherwise Specified
(Continued)
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
DD
= BV
DSS
45
V
DD
= BV
DSS
7.5
10.0
V
GS
, GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
4000
3000
30
2000
R
L
= 1.2Ω
I
G(REF)
= 1.0mA
V
GS
= 10V
0.75 BV
DSS
0.75 BV
DSS
0.50 BV
DSS
0.25 BV
DSS
0.50 BV
DSS
0.25 BV
DSS
5.0
15
2.5
1000
0
0
5
10
15
20
25
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0
20
I
G(REF)
I
G(ACT)
t, TIME (µs)
80
I
G(REF)
I
G(ACT)
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
P
R
G
-
I
AS
V
DD
t
P
V
DS
V
DD
+
0V
I
AS
0.01Ω
0
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
t
ON
V
DS
V
DS
V
GS
R
L
+
t
OFF
t
d(OFF)
t
r
t
f
90%
t
d(ON)
90%
DUT
R
GS
V
GS
-
V
DD
0
10%
90%
10%
V
GS
0
10%
50%
PULSE WIDTH
50%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
RFF70N06 Rev. A
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