LPC122x
32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and
8 kB SRAM
Rev. 2 — 26 August 2011
Product data sheet
1. General description
The LPC122x extend NXP's 32-bit ARM microcontroller continuum and target a wide
range of industrial applications in the areas of factory and home automation. Benefitting
from the ARM Cortex-M0 Thumb instruction set, the LPC122x have up to 50 % higher
code density compared to common 8/16-bit microcontroller performing typical tasks. The
LPC122x also feature an optimized ROM-based divide library for Cortex-M0, which offers
several times the arithmetic performance of software-based libraries, as well as highly
deterministic cycle time combined with reduced flash code size. The ARM Cortex-M0
efficiency also helps the LPC122x achieve lower average power for similar applications.
The LPC122x operate at CPU frequencies of up to 45 MHz.They offer a wide range of
flash memory options, from 32 kB to 128 kB. The small 512-byte page erase of the flash
memory brings multiple design benefits, such as finer EEPROM emulation, boot-load
support from any serial interface and ease of in-field programming with reduced on-chip
RAM buffer requirements.
The peripheral complement of the LPC122x includes a 10-bit ADC, two comparators with
output feedback loop, two UARTs, one SSP/SPI interface, one I
2
C-bus interface with
Fast-mode Plus features, a Windowed Watchdog Timer, a DMA controller, a CRC engine,
four general purpose timers, a 32-bit RTC, a 1 % internal oscillator for baud rate
generation, and up to 55 General Purpose I/O (GPIO) pins.
2. Features and benefits
Processor core
ARM Cortex-M0 processor, running at frequencies of up to 45 MHz (one wait state
from flash) or 30 MHz (zero wait states from flash). The LPC122x have a high
score of over 45 in CoreMark CPU performance benchmark testing, equivalent to
1.51/MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug (SWD).
System tick timer.
Memory
Up to 8 kB SRAM.
Up to 128 kB on-chip flash programming memory.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Includes ROM-based 32-bit integer division routines.
Clock generation unit
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy that can optionally be
used as a system clock.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
Clock output function with divider that can reflect the system oscillator clock, IRC
clock, main clock, and Watchdog clock.
Real-Time Clock (RTC).
Digital peripherals
Micro DMA controller with 21 channels.
CRC engine.
Two UARTs with fractional baud rate generation and internal FIFO. One UART with
RS-485 and modem support and one standard UART with IrDA.
SSP/SPI controller with FIFO and multi-protocol capabilities.
I
2
C-bus interface supporting full I
2
C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode. I
2
C-bus
pins have programmable glitch filter.
Up to 55 General Purpose I/O (GPIO) pins with programmable pull-up resistor,
open-drain mode, programmable digital input glitch filter, and programmable input
inverter.
Programmable output drive on all GPIO pins. Four pins support high-current output
drivers.
All GPIO pins can be used as edge and level sensitive interrupt sources.
Four general purpose counter/timers with four capture inputs and four match
outputs (32-bit timers) or two capture inputs and two match outputs (16-bit timers).
Windowed WatchDog Timer (WWDT); IEC-60335 Class B certified.
Analog peripherals
One 8-channel, 10-bit ADC.
Two highly flexible analog comparators. Comparator outputs can be programmed
to trigger a timer match signal or can be used to emulate 555 timer behavior.
Power
Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
Processor wake-up from Deep-sleep mode via start logic using 12 port pins.
Processor wake-up from Deep-power down and Deep-sleep modes via the RTC.
Brownout detect with three separate thresholds each for interrupt and forced reset.
Power-On Reset (POR).
Integrated PMU (Power Management Unit).
Unique device serial number for identification.
3.3 V power supply.
Available as 64-pin and 48-pin LQFP package.
LPC122X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
2 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
3. Applications
eMetering
Lighting
Industrial networking
Alarm systems
White goods
4. Ordering information
Table 1.
Ordering information
Package
Name
Description
Version
Type number
LPC1227FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm SOT314-2
LPC1226FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm SOT314-2
LPC1225FBD64/321 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm SOT314-2
LPC1225FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm SOT314-2
LPC1224FBD64/121 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm SOT314-2
LPC1224FBD64/101 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm SOT314-2
LPC1227FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
LPC1226FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
LPC1225FBD48/321 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
LPC1225FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
LPC1224FBD48/121 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
LPC1224FBD48/101 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
SOT313-2
SOT313-2
SOT313-2
SOT313-2
SOT313-2
SOT313-2
LPC122X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
3 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
4.1 Ordering options
Table 2.
Ordering options for LPC122x
Flash
Total UART
SRAM
2
2
2
2
2
2
2
2
2
2
2
2
I
2
C/
FM+
1
1
1
1
1
1
1
1
1
1
1
1
SSP/
SPI
1
1
1
1
1
1
1
1
1
1
1
1
ADC
GPIO Package
channels
8
8
8
8
8
8
8
8
8
8
8
8
55
39
55
39
55
55
39
39
55
55
39
39
LQFP64
LQFP48
LQFP64
LQFP48
LQFP64
LQFP64
LQFP48
LQFP48
LQFP64
LQFP64
LQFP48
LQFP48
Type number
LPC1227
LPC1227FBD64/301 128 kB 8 kB
LPC1227FBD48/301 128 kB 8 kB
LPC1226
LPC1226FBD64/301 96 kB
LPC1226FBD48/301 96 kB
LPC1225
LPC1225FBD64/321 80 kB
LPC1225FBD64/301 64 kB
LPC1225FBD48/321 80 kB
LPC1225FBD48/301 64 kB
LPC1224
LPC1224FBD64/121 48 kB
LPC1224FBD64/101 32 kB
LPC1224FBD48/121 48 kB
LPC1224FBD48/101 32 kB
4 kB
4 kB
4 kB
4 kB
8 kB
8 kB
8 kB
8 kB
8 kB
8 kB
LPC122X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
4 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
XTALIN
XTALOUT
RESET
SWD
LPC122x
IRC, OSCILLATORS
BOD
TEST/DEBUG
INTERFACE
POR
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
clocks and controls
CLKOUT
ARM
CORTEX-M0
MICRO DMA
CONTROLLER
system
bus
master
32/48/64/80/
96/128 kB
FLASH
slave
4/8 kB
SRAM
slave
ROM
slave
AHB-LITE BUS
slave
GPIO ports
HIGH-SPEED
GPIO
slave
AHB-APB
BRIDGE
slave
CRC
ENGINE
SCK
SSEL
MISO
MOSI
RXD0
TXD0
DTR0, DSR0, CTS0,
DCD0, RI0, RTS0
RXD1
TXD1
SCL
SDA
4 × MAT
4 × CAP
4 × MAT
4 × CAP
2 × MAT
2 × CAP
2 × MAT
2 × CAP
SSP/SPI
10-bit ADC
AD[7:0]
ACMP0_I[3:0]
ACMP1_I[3:0]
ACMP0_O
ACMP1_O
VREF_CMP
UART0 RS-485
COMPARATOR0/1
UART1
I
2
C
RTC
WINDOWED WDT
IOCONFIG
32 kHz OSCILLATOR
RTCXOUT
RTCXIN
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
SYSTEM CONTROL
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
MICRO DMA REGISTERS
Grey-shaded blocks represent peripherals
with connection to the micro DMA controller
002aaf269
Fig 1.
LPC122x block diagram
LPC122X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
5 of 61
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