5962-01A1801VYC datasheet, PDF

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5962-01A1801VYC: Description16-Bit Flow-Through EDAC Error Detection And Correction unit; File Size154KB，17 Pages; ManufacturerAtmel (Microchip)

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16-Bit Flow-Through EDAC Error Detection And Correction unit

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29C516E

16–Bit Flow–Through EDAC

Error Detection And Correction unit

1. Introduction

The 29C516E

Atmel

EDAC is a very low power

flow–through 16–bit Error Detection And Correction unit

(EDAC) with two user data buses. The EDAC is used in

a high integrity system for monitoring and correction of

data values coming from the memory space. During a

processor write cycle, at each memory location (16–bit

width), EDAC calculated checkword (6 or 8–bit width) is

added. When performing a read operation from memory,

the 29C516E verifies the entire checkword and data

combination. It detects and can correct 100% of all the

single–bit errors and it detects all double–bit errors.

When the 29C516E uses 6–checkbit, it can detect any

error on any single 4–bit memory chip. The 8–check–bit

option gives the additional capability to detect all errors

on any single 8–bit memory chip. All the errors are

signaled to the master system (via 2 error Flags) in order

to allow the processor to make the required action.

The 29C516E operates in two possible modes: corrected

or detected mode. In the corrected mode, the single–bit in

error is complemented (corrected). Then, the available

entire data is placed on the output port and the Correctable

Error Flag is set. In case of double–bit errors (or more),

the corrupted data is placed on the output port and the

Uncorrectable Error Flag is set. Note that when there is

more than two errors, then some bit patterns may appear

as possible correctable errors. Therefore, if the

environment produces this type of error, the EDAC must

be used in detect and provide no automatic correction.

Data and syndrome analysis must be done.

The 29C516E acts as a data buffer for

µP–memory

interfacing. A flow–through EDAC is placed in the data

bus path, between the processor and the memory to be

protected. This component is able to serve two different

users of one memory space. So, it forms the interface

between the 22/24–bit (16+6/16+8) memory data bus and

the two 16–bit processor data busses with a high drive

capability (–12.8 mA). The two data ports can be used to

create a dual port bus in front of memory space. The

User–1(2) can transfer data from/to the memory or

from/to the User–2(1), by–passing the memory. During

read or write memory cycles processed by the User–1(2),

the User–2(1) have the possibility to listen the

transferred data.

2. Features

Very Low Power CMOS

16–Bit operation with 6 or 8 Check Bits

Fast Error Detection : 31 ns (max.)

Fast Error Correction : 32 ns (max.)

Corrects all Single–Bit Errors

Detects all Double–Bit Errors

Detects some Multi–Bit Errors

Detects Chip Errors (x1, x4 & x8 RAM Format)

Correctable and Uncorrectable Error Flags

Two User Data Buses

User to User Transfer and Listening operation

High Drive Capability on Buses : –12.8 mA

TTL Compatible

Single 5V

±10%

Power Supply

100 Pin Multilayer Quad Flat Pack

(Flat leaded or L leaded).

Atmel Corporation

Rev.

(03

2007)

5962-01A1801VYC Related Products

	5962-01A1801VYC	29C516E_07	5962-01A1801QYC	MMFR-26C516E-31-E
Description	16-Bit Flow-Through EDAC Error Detection And Correction unit	16-Bit Flow-Through EDAC Error Detection And Correction unit	16-Bit Flow-Through EDAC Error Detection And Correction unit	16-Bit Flow-Through EDAC Error Detection And Correction unit

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