29C516E
16–Bit Flow–Through EDAC
Error Detection And Correction unit
1. Introduction
The 29C516E
Atmel
EDAC is a very low power
flow–through 16–bit Error Detection And Correction unit
(EDAC) with two user data buses. The EDAC is used in
a high integrity system for monitoring and correction of
data values coming from the memory space. During a
processor write cycle, at each memory location (16–bit
width), EDAC calculated checkword (6 or 8–bit width) is
added. When performing a read operation from memory,
the 29C516E verifies the entire checkword and data
combination. It detects and can correct 100% of all the
single–bit errors and it detects all double–bit errors.
When the 29C516E uses 6–checkbit, it can detect any
error on any single 4–bit memory chip. The 8–check–bit
option gives the additional capability to detect all errors
on any single 8–bit memory chip. All the errors are
signaled to the master system (via 2 error Flags) in order
to allow the processor to make the required action.
The 29C516E operates in two possible modes: corrected
or detected mode. In the corrected mode, the single–bit in
error is complemented (corrected). Then, the available
entire data is placed on the output port and the Correctable
Error Flag is set. In case of double–bit errors (or more),
the corrupted data is placed on the output port and the
Uncorrectable Error Flag is set. Note that when there is
more than two errors, then some bit patterns may appear
as possible correctable errors. Therefore, if the
environment produces this type of error, the EDAC must
be used in detect and provide no automatic correction.
Data and syndrome analysis must be done.
The 29C516E acts as a data buffer for
µP–memory
interfacing. A flow–through EDAC is placed in the data
bus path, between the processor and the memory to be
protected. This component is able to serve two different
users of one memory space. So, it forms the interface
between the 22/24–bit (16+6/16+8) memory data bus and
the two 16–bit processor data busses with a high drive
capability (–12.8 mA). The two data ports can be used to
create a dual port bus in front of memory space. The
User–1(2) can transfer data from/to the memory or
from/to the User–2(1), by–passing the memory. During
read or write memory cycles processed by the User–1(2),
the User–2(1) have the possibility to listen the
transferred data.
2. Features
D
D
D
D
D
D
D
D
Very Low Power CMOS
16–Bit operation with 6 or 8 Check Bits
Fast Error Detection : 31 ns (max.)
Fast Error Correction : 32 ns (max.)
Corrects all Single–Bit Errors
Detects all Double–Bit Errors
Detects some Multi–Bit Errors
Detects Chip Errors (x1, x4 & x8 RAM Format)
D
D
D
D
D
D
D
Correctable and Uncorrectable Error Flags
Two User Data Buses
User to User Transfer and Listening operation
High Drive Capability on Buses : –12.8 mA
TTL Compatible
Single 5V
±10%
Power Supply
100 Pin Multilayer Quad Flat Pack
(Flat leaded or L leaded).
Atmel Corporation
Rev.
E
(03
2007)
1
29C516E
3. Interface
3.1. Functional Diagram
Figure 1.Functional Diagram
8
CORRECT
SYNCHK
MEM1
EN1
RD/WR1
CHECK BIT
GENERATOR
16
I/O
BUFFER
8
MC[0..7]
8
U1D[0..15]
U2/U1
TRANS
U2D[0..15]
16
16
I/O
BUFFER
16
CONTROLLER
16
16
I/O
BUFFER
16
29C516E
RD/WR2
EN2
MEM2
16
16
16
I/O
BUFFER
16
MD[0..15]
CERR
NCERR
N22
SYNDROME
DECODER
8
SYNDROME
GENERATOR
3.2. Block Diagram
Figure 2.Block Diagram
VCC
CORRECT
SYNCHK
N22
U1/U2
TRANS
U1D[0..15] MC[0..7]
EN1
MEM1
RD/WR1 MD[0..15]
U2D[0..15]
EN2
MEM2
RD/WR2
GND
29C516E
CERR
NCERR
2
Rev.
E
(03
2007)
29C516E
3.3. Pin Configuration for multilayer quad Flat–pack (flat or L leaded)
Figure 3.Pin Configuration
index corner
nc
nc
MEM2
Gnd
U2D[15]
U2D[14]
U2D[13]
U2D[12]
Vcc
U2D[11]
U2D[10]
U2D[9]
U2D[8]
Gnd
U2D[7]
U2D[6]
U2D[5]
U2D[4]
Vcc
U2D[3]
U2D[2]
U2D[1]
U2D[0]
Gnd
NCERR
CERR
N22
U1D[15]
nc
nc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Vcc
RD/WR2
CORRECT
SYNCHK
TRANS
U2/U1
EN2
Gnd
Gnd
MC[7]
MC[6]
MC[5]
MC[4]
Vcc
MC[3]
MC[2]
MC[1]
MC[0]
nc
nc
MQFPF100
or
MQFPL100
(Top view)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
nc
nc
Gnd
MD[15]
MD[14]
MD[13]
MD[12]
Vcc
MD[11]
MD[10]
MD[9]
MD[8]
Gnd
MD[7]
MD[6]
MD[5]
MD[4]
Vcc
MD[3]
MD[2]
MD[1]
MD[0]
Gnd
MEM1
EN1
RD/WR1
Vcc
U1D[0]
nc
nc
nc
Vcc
U1D[14]
U1D[13]
U1D[12]
Gnd
U1D[11]
U1D[10]
U1D[9]
U1D[8]
Vcc
U1D[7]
U1D[6]
U1D[5]
U1D[4]
Gnd
U1D[3]
U1D[2]
U1D[1]
nc
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Rev.
E
(03
2007)
3
29C516E
3.4. Pin Description
Table 1:
Name
Pin Description
I/O
Active
Description
Buses
U1D[0..15]
U2D[0..15]
ΜD[0..15]
ΜC[0..7]
Error Flags
CERR
NCERR
26
25
O
O
Low
Low
Correctable Error
Uncorrectable Error
53,49..47,45..42,40..37,35..33,28
23..20,18..15,13..10,8..5
59..62,64..67,69..72,74..77
83..86,88..91
I/O*
I/O*
I/O*
I/O*
High
High
High
High
User 1 Data Bus
User 2 Data Bus
Memory Data Bus
Memory Check–bit Bus
General Control Signals
CORRECT
SYNCHK
N22
TRANS
98
97
27
96
I*
I*
I*
I*
High
Low
High
H/L
When active, the EDAC is in CORRECT mode. If low,
the EDAC is in DETECT mode.
Selects the Syndrome bits (high byte) and the Check–bits
(low byte) to be driven on the selected User Data Bus.
When active, the EDAC uses 6 check–bits. If low, the
EDAC uses 8 check–bits in memory read.
Selects the Data path to be used. If high, the EDAC
access the memory, if low, the EDAC access the transfer
buffer.
Selects who is the master of User 1 and User 2. The
master is responsible for applying RD/WRx, MEMx, and
ENx signals in a correct way.
U2/U1
95
I*
H/L
User 1 Control Signals
RD/WRT
EN1
MEM1
55
56
57
I*
I*
I*
H/L
Low
Low
User 1 Read/Write signal
User 1 Output Enable
User 1 Memory Select
User 1 Control Signals
RD/WR2
EN2
MEM2
Power (Buffers)
VCC
B
GND
B
Power (Core)
VCC
C
GND
C
100
93
I
I
–
–
Core supply (5 V nominal)
Core 0 V reference
9,19,32,41,54,63,73,87
4,14,24,36,46,58,68,78,92
I
I
–
–
Buffers supply (5 V nominal)
Buffers 0 V nominal reference
99
94
3
I*
I*
I*
H/L
Low
Low
User 2 Read/Write signal
User 2 Output Enable
User 2 Memory Select
* Pull–up buffers
4
Rev.
E
(03
2007)
29C516E
4. Check–Bit Generation
The Check–bit Generator produces 8 check–bits
(whatever N22 value) from the incoming User Data Word
UxD[0..15] according the Table 2.
Example: to create check–bit 0, bit 13, 12, 8, 7, 6, 5, 4 and
0 of the Data Word are XORed together.
If memory devices 8–bit wide are used, 24 bits
(MD[0..15] & MC[0..7]) are stored to give error
detection. But if memory devices 1–bit or 4–bit wide are
used, 22 bits (MD[0..15] & MC[0..5]) are stored to give
error detection.
Table 2: Check Bit Generation (indicates a bit of UxD bus used in the XOR/NXOR)
MC[..]
PARITY
15
0
1
2
3
Even(XOR)
Even(XOR)
Odd(NXOR)
Odd(NXOR)
x
x
x
x
x
x
14
13
x
12
x
x
x
x
x
11
10
9
UxD[..]
8
x
x
7
x
6
x
x
x
x
5
x
4
x
x
x
x
x
x
x
x
x
x
x
3
2
1
0
x
4
5
6
7
Even(XOR)
Even(XOR)
Even(XOR)
Odd(NXOR)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5. Syndrome Generation
The syndrome Generator produces 8 syndrome–bits
(whatever N22 value) from the incoming Memory Data
Word MD[0..15] and the associated Check–bits MC[0..7]
(or MC[0..5]) according the Table 3.
Syndrome–bit SY[x] is the XOR of the generated
Check–bit MC[x] with the generation of Chek–bit on
MD[..].
Example: to create syndrome–bit 3, first the bit 14,
13, 10, 4, 3, 2, 1 and 0 of the Data Word
(MD[14,13,10,4,3,2,1,0]) are NXORed. Then, the result
is XORed with the associated Check–bit (MC[3]) of the
Check–byte read in the same time as Data Word is
checked.
If the memory uses x8 devices, then the bits should be
physically divided as follows: MC[0..7], MD[0..7] and
MD[8..15] . For x4 organization, the bits should be
divided MC[0..2]+MC[6], MC[3..5]+MC[7], MD[0..3],
MD[4..7], MD[8..11] and MD[12..15].
Table 3: Syndrome Bit Generation (indicates a bit of MD and MC buses used in the XOR/NXOR)
SY[..]
PARITY
15
0
1
2
3
EVEN(XOR)
EVEN(XOR)
ODD(NXOR)
ODD(NXOR)
x
x
x
x
x
x
14
13
x
12
x
x
x
x
x
11
10
9
MD[..]
8
x
x
7
x
6
x
x
x
x
5
x
4
x
x
x
x
x
x
x
x
x
x
x
x
x
3
2
1
0
x
x
7
5
4
MC[..]
3
6
2
1
0
x
4
5
EVEN(XOR)
EVEN(XOR)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
6
7
EVEN(XOR)
ODD(NXOR)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Rev.
E
(03
2007)
5
Microchip MCU
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